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Product Specification
Summary of QProTM VirtexTM-II Features
* * * * * * Industry First Military Grade Platform FPGA Solution Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) 100% Factory Tested Guaranteed over the full military temperature range (-55 C to +125 C) Ceramic and Plastic Wire-Bond and Flip-Chip Grid Array Packages IP-Immersion Architecture - Densities from 1M to 6M system gates - 300+ MHz internal clock speed (Advance Data) - 622+ Mb/s I/O (Advance Data) SelectRAMTM Memory Hierarchy - 2.5 Mb of dual-port RAM in 18 Kbit block SelectRAM resources - Up to 1 Mb of distributed SelectRAM resources High-Performance Interfaces to External Memory - DRAM interfaces
* * * SDR/DDR SDRAM Network FCRAM Reduced Latency DRAM SDR/DDR SRAM QDR SRAM
*
Fourth generation segmented routing structure Predictable, fast routing delay, independent of fanout SelectIOTM-Ultra Technology - Up to 824 user I/Os - 19 single-ended and six differential standards - Programmable sink current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI compliant (32/33 MHz) at 3.3V - Differential Signaling
* * * * * 622 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers Bus LVDS I/O Lightning Data Transport (LDT) I/O with current driver buffers Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O Built-in DDR input and output registers
*
*
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Proprietary high-performance SelectLink Technology
* * * High-bandwidth data path Double Data Rate (DDR) link Web-based HDL generation methodology
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SRAM interfaces
* *
*
*
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- CAM interfaces Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 67,584 internal registers/latches with Clock Enable - Up to 67,584 look-up tables (LUTs) or cascadable 16-bit shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and sum-of-products support - Internal 3-state busing High-Performance Clock Management Circuitry - Up to 12 DCM (Digital Clock Manager) modules
* * * Precise clock de-skew Flexible frequency synthesis High-resolution phase shifting
*
*
* * *
Supported by Xilinx Foundation SeriesTM and Alliance SeriesTM Development Systems - Integrated VHDL and Verilog design flows - Compilation of 10M system gates designs - Internet Team Design (ITD) tool SRAM-Based In-System Configuration - Fast SelectMAP configuration - Triple Data Encryption Standard (DES) security option (Bitstream Encryption) - IEEE 1532 support - Partial reconfiguration - Unlimited reprogrammability - Readback capability 0.15 m 8-Layer Metal Process with 0.12 m High-Speed Transistors 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies IEEE 1149.1 Compatible Boundary-Scan Logic Support
*
- 16 global clock multiplexer buffers Active Interconnect Technology
(c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Table 1: Virtex-II Field-Programmable Gate Array Family Members CLB (1 CLB = 4 slices = Max 128 bits) System Gates 1M 3M 6M Array Row x Col. 40 x 32 64 x 56 96 x 88 Maximum Distributed RAM Kbits 160 448 1,056 Multiplier Blocks 40 96 144 SelectRAM Blocks 18 Kbit Blocks 40 96 144 Max RAM (Kbits) 720 1,728 2,592 Max I/O Pads(1) 432 720 1,104
Device XQ2V1000 XQ2V3000 XQ2V6000
Slices 5,120 14,336 33,792
DCMs 8 12 12
Notes: 1. See details in Table 2, "Maximum Number of User I/O Pads".
General Description
The Virtex-II family includes platform FPGAs developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 m/0.12 m CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 8 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, the QPro Virtex-II family comprises three members, ranging from 1M to 6M system gates. wire-bond interconnects, flip-chip interconnect is used in some of the CGA offerings. The use of flip-chip interconnect offers more I/Os than is possible in wire-bond versions of the similar packages. Flip-chip construction offers the combination of high pin count with high thermal capacity. Table 2 shows the maximum number of user I/Os available. The Virtex-II device/package combination table (Table 5 on page 5) details the maximum number of I/Os for each device and package using wire-bond or flip-chip technology. Table 2: Maximum Number of User I/O Pads Device XQ2V1000 XQ2V3000 Wire-Bond 328 516 Flip-Chip 824
Packaging
Offerings include ball grid array (BGA) packages with 1.00 mm and 1.27 mm pitches. In addition to traditional
XQ2V6000
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs). Programmable I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs.
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DCM Global Clock Mux
DCM
IOB
Configurable Logic
Programmable I/Os CLB Block SelectRAM Multiplier
DS031_28_100900
Figure 1: Virtex-II Architecture Overview The internal configurable logic includes four major elements organized in a regular array: * Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large 18 Kbit storage elements of dual-port RAM. Multiplier blocks are 18-bit x 18-bit dedicated multipliers. DCM (Digital Clock Manager) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, coarse- and fine-grained clock phase shifting. * * Input block with an optional single-data-rate or double-data-rate (DDR) register Output block with an optional single-data-rate or DDR register, and an optional 3-state buffer, to be driven directly or through a single or DDR register Bidirectional block (any combination of input and output configurations)
*
* * *
These registers are either edge-triggered D-type flip-flops or level-sensitive latches. IOBs support the following single-ended I/O standards: * * * * * * * LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI compatible (33 MHz) at 3.3V CardBus compliant (33 MHz) at 3.3V GTL and GTLP HSTL (Class I, II, III, and IV) SSTL (3.3V and 2.5V, Class I and II) AGP-2X
A new generation of programmable routing resources called Active Interconnect Technology interconnects all of these elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. The overall programmable interconnection is hierarchical and designed to support high-speed designs. All programmable elements, including the routing resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements.
The digitally controlled impedance (DCI) I/O feature automatically provides on-chip termination for each I/O element. The IOB elements also support the following differential signaling I/O standards: * * * * * LVDS BLVDS (Bus LVDS) ULVDS LDT LVPECL
Virtex-II Features
This section briefly describes Virtex-II features.
Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the routing resources.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
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Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers. Each slice is equivalent and contains: * * * * * * * Two function generators (F and G) Two storage elements Arithmetic logic gates Large multiplexers Wide function capability Fast carry look-ahead chain Horizontal cascade chain (OR gate)
Up to 12 DCM blocks are available. To generate de-skewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. Fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clock output frequency equal to any M/D ratio of the input clock frequency, where M and D are two integers. For the exact timing parameters, see QPro Virtex-II Switching Characteristics, page 51. Virtex-II devices have 16 global clock MUX buffers with up to eight clock nets per quadrant. Each global clock MUX buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. Each DCM block is able to drive up to four of the 16 global clock MUX buffers.
The function generators F and G are configurable as 4-input look-up tables (LUTs), as 16-bit shift registers, or as 16-bit distributed SelectRAM memory. In addition, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources.
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance of high-speed designs. There are a total of 16 global clock lines with eight available per quadrant. In addition, 24 vertical and horizontal long lines per row or column as well as massive secondary and local routing resources provide fast interconnect. Virtex-II buffered interconnects are relatively unaffected by net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources for each row or column include: * * * * 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions)
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of dual-port RAM, programmable from 16K x 1 bit to 512 x 36 bits, in various depth and width configurations. Each port is totally synchronous and independent, offering three "read-during-write" modes. Block SelectRAM memory is cascadable to implement large embedded storage blocks. Supported memory configurations for dual-port and single-port modes are shown in Table 3. Table 3: Dual-Port And Single-Port Configurations 16K x 1 bit 8K x 2 bits 4K x 4 bits 2K x 9 bits 1K x 18 bits 512 x 36 bits
A multiplier block is associated with each SelectRAM memory block. The multiplier block is a dedicated 18 x 18-bit multiplier and is optimized for operations based on the block SelectRAM content on one port. The 18 x 18 multiplier can be used independently of the block SelectRAM resource. Read/multiply/accumulate operations and DSP filter structures are extremely efficient. Both the SelectRAM memory and the multiplier resource are connected to four switch matrices to access the general routing resources.
Boundary Scan
Boundary-scan instructions and associated data registers support a standard methodology for accessing and configuring Virtex-II devices that complies with IEEE standards 1149.1 -- 1993 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II device performs its intended mission even while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instructions are also supported.
Global Clocking
The DCM and global clock multiplexer buffers provide a complete solution for designing high-speed clocking schemes.
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Virtex-II Device/Package Combinations and Maximum I/O
Wire-bond and flip-chip packages are available. Table 4 shows the maximum possible number of user I/Os in wire-bond and flip-chip packages. Table 5 shows the number of available user I/Os for all device/package combinations. * * FG denotes wire-bond fine-pitch Plastic BGA (1.00 mm pitch). BG denotes wire-bond standard Plastic BGA (1.27 mm pitch). * * CG denotes wire-bond fine-pitch Hermetic Ceramic Column Grid Array (1.27 mm pitch). CF denotes flip-chip fine-pitch non-Hermetic Ceramic Column Grid Array (1.00 mm pitch).
The number of I/Os per package include all user I/Os except the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, and RSVD) and VBATT.
Table 4: Package Information Package Pitch (mm) Size (mm) FG456 1.00 23 x 23 BG575 1.27 31 x 31 BG728 & CG717 1.27 35 x 35 CF1144 1.00 35 x 35
Table 5: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os Available I/Os Package FG456 BG575 BG728 CG717 CF1144 XQ2V1000 324 328 XQ2V3000 516 516 XQ2V6000 824
Notes: 1. The BG728 and CG717 packages are pinout (footprint) compatible. 2. The CF1144 is pinout (footprint) compatible with the FF1152.
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Virtex-II Ordering Information
Example:
Device Type Speed Grade(1)
XQ2V3000 -4 CG 717 M
Temperature Range/Grade Number of Pins Package Type
Device Ordering Options
Device Type XQ2V1000 XQ2V3000 XQ2V6000 FG456 BG575 BG728 CG717 CF1144
Package 456-ball Plastic Fine Pitch BGA Package 575-ball Plastic BGA Package 728-ball Plastic BGA Package 717-column Ceramic CGA Package 1144-column Ceramic Flip-Chip Package M N
Grade Military Ceramic Military Plastic
Temperature TC = -55 C to +125 C TJ = -55 C to +125 C
Notes: 1. -4 only supported speed grade.
Valid Ordering Combinations
M Grade XQ2V3000-4CG717M XQ2V6000-4CF1144M(1) N Grade XQ2V1000-4FG456N XQ2V1000-4BG575N XQ2V3000-4BG728N
Notes: 1. CF1144 is non-Hermetic Ceramic.
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Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as an input and/or an output for single-ended I/Os. Two IOBs can be used as a differential pair. A differential pair is always connected to the same switch matrix, as shown in Figure 2. IOB blocks are designed for high-performance I/Os, supporting 19 single-ended standards, as well as differential signaling with LVDS, LDT, Bus LVDS, and LVPECL. Table 6: Supported Single-Ended I/O Standards
I/O Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15
IOB PAD4 Differential Pair IOB PAD3 Switch Matrix IOB PAD2 Differential Pair IOB PAD1
DS031_30_101600
Output VCCO 3.3 3.3 2.5 1.8 1.5 3.3 3.3 3.3 Note 1 Note 1 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5 3.3 3.3 3.3
Input VCCO 3.3 3.3 2.5 1.8 1.5 3.3 3.3 3.3 Note 1 Note 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Input VREF N/A N/A N/A N/A N/A N/A N/A N/A 0.8 1.0 0.75 0.75 0.9 0.9 0.9 0.9 1.1 1.1 1.25 1.25 1.5 1.5 1.32
Board Termination Voltage (VTT) N/A N/A N/A N/A N/A N/A N/A N/A 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.25 1.25 1.5 1.5 N/A
PCI33_3 PCI66_3 PCI-X GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I HSTL_II HSTL_III HSTL_IV SSTL2_I SSTL2_II SSTL3_I SSTL3_II AGP-2X/AGP
Figure 2: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and outputs that support a wide variety of I/O signaling standards. In addition to the internal supply voltage (VCCINT = 1.5V), output driver supply voltage (VCCO) is dependent on the I/O standard (see Table 6). An auxiliary supply voltage (VCCAUX = 3.3 V) is required, regardless of the I/O standard used. For exact supply voltage absolute maximum ratings, see DC Input and Output Levels.
Notes: 1. VCCO of GTL or GTLP should not be lower than the termination voltage or the voltage seen at the I/O pad.
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Table 7: Supported Differential Signal I/O Standards
I/O Standard LVPECL_33 LDT_25 LVDS_33 LVDS_25 LVDSEXT_33 LVDSEXT_25 BLVDS_25 ULVDS_25 Output VCCO 3.3 2.5 3.3 2.5 3.3 2.5 2.5 2.5 Input VCCO N/A N/A N/A N/A N/A N/A N/A N/A Input VREF N/A N/A N/A N/A N/A N/A N/A N/A Output VOD 490 mV to 1.22V 0.430 - 0.670 0.250 - 0.400 0.250 - 0.400 0.330 - 0.700 0.330 - 0.700 0.250 - 0.450 0.430 - 0.670
Table 8: Supported DCI I/O Standards
I/O Standard LVDCI_33 (1) LVDCI_DV2_33 (1) LVDCI_25 (1) LVDCI_DV2_25 (1) LVDCI_18 (1) LVDCI_DV2_18 (1) LVDCI_15 (1) LVDCI_DV2_15 (1) GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI Output VCCO 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5 3.3 3.3 Input VCCO 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.5 1.5 1.5 1.5 1.5 N/A N/A N/A N/A 2.5 2.5 3.3 3.3 Input VREF N/A N/A N/A N/A N/A N/A N/A N/A 0.8 1.0 0.75 0.75 0.9 0.9 0.9 0.9 1.1 1.1 1.25 1.25 1.5 1.5 Termination Type Series Series Series Series Series Series Series Series Single Single Split Split Single Single Split Split Single Single Split Split Split Split
All of the user IOBs have fixed-clamp diodes to VCCO and to ground. As outputs, these IOBs are not compatible or compliant with 5V I/O standards. As inputs, these IOBs are not normally 5V tolerant, but can be used with 5V I/O standards when external current-limiting resistors are used. For more details, see the "5V Tolerant I/Os" Tech Topic at
http://www.xilinx.com.
Table 8 lists supported I/O standards with Digitally Controlled Impedance. See Digitally Controlled Impedance (DCI), page 13.
IOB DDR mux Reg OCK1 Reg ICK1 Reg OCK2 3-State Reg ICK2 DDR mux Reg OCK1 PAD Reg OCK2 Output Input
HSTL_IV_DCI SSTL2_I_DCI (2) SSTL2_II_DCI (2) SSTL3_I_DCI (2) SSTL3_II_DCI (2)
Notes: 1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. These are SSTL compatible.
Logic Resources
IOB blocks include six storage elements, as shown in Figure 3.
DS031_29_100900
Figure 3: Virtex-II IOB Block
Each storage element can be configured either as an edge-triggered D-type flip-flop or as a level-sensitive latch. On the input, output, and 3-state path, one or two DDR registers can be used. Double data rate is directly accomplished by the two registers on each path, clocked by the rising edges (or falling edges) from two different clock nets. The two clock signals are generated by the DCM and must be 180 degrees out of phase, as shown in Figure 4. There are two input, output, and 3-state data signals, each being alternately clocked out.
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DCM 180 0 FDDR D1 Q1 CLOCK CLK1 D1 Q1 CLK1 FDDR
DDR MUX
Q
DDR MUX
Q
D2 Q2 CLK2
D2 Q2 CLK2
(50/50 duty cycle clock)
DS031_26_100900
Figure 4: Double Data Rate Registers The DDR mechanism shown in Figure 4 can be used to mirror a copy of the clock on the output. This is useful for propagating a clock along the data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load. Virtex-II devices can produce many copies of a clock with very little skew. Each group of two registers has a clock enable signal (ICE for the input registers, OCE for the output registers, and TCE for the 3-state registers). The clock enable signals are active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. Each IOB block has common synchronous or asynchronous set and reset (SR and REV signals). SR forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic "1". SRLOW forces a logic "0". When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition. The initial state after configuration or global initialization state is defined by a separate INIT0 and INIT1 attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1. For each storage element, the SRHIGH, SRLOW, INIT0, and INIT1 attributes are independent. Synchronous or asynchronous set/reset is consistent in an IOB block. All the control signals have independent polarities. Any inverter placed on a control input is automatically absorbed. Each register or latch (independent of all other registers or latches) (see Figure 5) can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear)
The synchronous reset overrides a set, and an asynchronous clear overrides a preset.
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(O/T) 1 Attribute INIT1 INIT0 SRHIGH SRLOW
FF LATCH (O/T) CE (O/T) CLK1 SR Shared by all registers REV FF LATCH D2 Q2 D1 Q1
CE CK1 SR REV FF1 DDR MUX FF2 (OQ or TQ)
(O/T) CLK2
CE CK2 SR REV
Attribute INIT1 INIT0 SRHIGH SRLOW
(O/T) 2
Reset Type SYNC ASYNC
DS031_25_110300
Figure 5: Register/Latch Configuration in an IOB Block
Input/Output Individual Options
Each device pad has optional pull-up and pull-down resistors in all SelectI/O-Ultra configurations. Each device pad has an optional weak-keeper in LVTTL, LVCMOS, and PCI SelectI/O-Ultra configurations, as illustrated in Figure 6.
VCCO OBUF Clamp Diode
Values of the optional pull-up and pull-down resistors are in the range 10 - 60 K which is the specification for VCCO , when operating at 3.3V (from 3.0V to 3.6V only). The clamp diode is always present, even when power is not.
VCCO Program Current 10-60K
Weak Keeper
PAD VCCO 10-60K VCCAUX = 3.3V VCCINT = 1.5V IBUF
DS031_23_011601
Program Delay
Figure 6: LVTTL, LVCMOS, or PCI SelectI/O-Ultra Standards
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QPro Virtex-II 1.5V Military QML Platform FPGAs LVTTL sinks and sources current up to 24 mA. The current is programmable for LVTTL and LVCMOS SelectI/O-Ultra standards (see Table 9). Drive-strength and slew-rate controls for each output driver minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew-rate controls are not available.
The optional weak-keeper circuit is connected to each output. When selected, this circuit monitors the voltage on the pad and weakly drives the pin High or Low. If the pin is connected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Pull-up or pull-down resistors override the weak-keeper circuit.
Table 9: LVTTL and LVCMOS Programmable Currents (Sink and Source) SelectI/O-Ultra LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 2 mA 2 mA 2 mA 2 mA 2 mA Programmable Current (Worst-Case Guaranteed Minimum) 4 mA 4 mA 4 mA 4 mA 4 mA 6 mA 6 mA 6 mA 6 mA 6 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 16 mA 16 mA 16 mA 16 mA 16 mA 24 mA 24 mA 24 mA n/a n/a
Figure 7 shows the SSTL2, SSTL3, and HSTL configurations. HSTL can sink current up to 48 mA. (HSTL IV)
VCCO OBUF Clamp Diode
pins. When HSWAP_EN is driven Low, the pull-up resistors are activated on user I/O pins. All Virtex-II IOBs support IEEE 1149.1 compatible boundary-scan testing.
Input Path
The Virtex-II IOB input path routes input signals directly to internal logic and/or through an optional input flip-flop or latch, or through the DDR input registers. An optional delay element at the D-input of the storage element eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the Virtex-II device, and when used, ensures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in the same bank. See I/O Banking description below.
PAD
VREF
VCCAUX = 3.3V VCCINT = 1.5V
DS031_24_100900
Figure 7: SSTL or HSTL SelectI/O-Ultra Standards All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Virtex-II devices use two memory cells to control the configuration of an I/O as an input. This is to reduce the probability of an I/O configured as an input from flipping to an output when subjected to a single event upset (SEU) in space applications. Prior to configuration, all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive. The dedicated pin HSWAP_EN controls the pull-up resistors prior to configuration. By default, HSWAP_EN is driven High, which disables the pull-up resistors on user I/O
Output Path
The output path includes a 3-state output buffer that drives the output signal onto the pad. The output and/or the 3-state signal can be routed to the buffer directly from the internal logic or through an output/3-state flip-flop or latch, or through the DDR output/3-state registers. Each output driver can be individually programmed for a wide range of low-voltage signaling standards. In most signaling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in the same bank. See I/O Banking description below.
I/O Banking
Some of the I/O standards described above require VCCO and VREF voltages. These voltages are externally supplied
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QPro Virtex-II 1.5V Military QML Platform FPGAs and connected to device pins that serve groups of IOB blocks, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from dividing each edge of the FPGA into two banks, as shown in Figure 8 and Figure 9. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use.
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VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All VREF pins for the largest device anticipated must be connected to the VREF voltage and are not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or, if necessary, they can be connected to VCCO to permit migration to a larger device.
Bank 0 Bank 7
Bank 1 Bank 2
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different input, output, and bidirectional standards in the same bank: 1. Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank.
Compatible example: SSTL2_I and LVDS_25_DCI outputs Incompatible example: SSTL2_I (output VCCO = 2.5V) and LVCMOS33 (output VCCO = 3.3V) outputs
Bank 6
Bank 5
Bank 4
ug002_c2_014_112900
Bank 3
Figure 8: Virtex-II I/O Banks: Top View for Wire-Bond Packages (CS, FG, & BG) Some input standards require a user-supplied threshold voltage (VREF), and certain user-I/O pins are automatically configured as VREF inputs. Approximately one in six of the I/O pins in the bank assume this role.
2. Combining input standards only. Input standards with the same input VCCO and input VREF requirements can be combined in the same bank.
Compatible example: LVCMOS15 and HSTL_IV inputs Incompatible example: LVCMOS15 (input VCCO = 1.5V) and LVCMOS18 (input VCCO = 1.8V) inputs Incompatible example: HSTL_I_DCI_18 (VREF = 0.9V) and HSTL_IV_DCI_18 (VREF = 1.1V) inputs
Bank 1 Bank 2
Bank 0 Bank 7
3. Combining input standards and output standards. Input standards and output standards with the same input VCCO and output VCCO requirement can be combined in the same bank.
Compatible example: LVDS_25 output and HSTL_I input Incompatible example: LVDS_25 output (output VCCO = 2.5V) and HSTL_I_DCI_18 input (input VCCO = 1.8V)
Bank 3
Bank 4
Bank 5
Bank 6
ds031_66_112900
Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip Packages (FF & BF) VREF pins within a bank are interconnected internally, and consequently only one VREF voltage can be used within each bank. However, for correct operation, all VREF pins in the bank must be connected to the external reference voltage source. The VCCO and the VREF pins for each bank appear in the device pinout tables. Within a given package, the number of
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4. Combining bidirectional standards with input or output standards. When combining bidirectional I/O with other standards, make sure the bidirectional standard can meet rules 1 through 3 above. 5. Additional rules for combining DCI I/O standards. a. No more than one Single Termination type (input or output) is allowed in the same bank.
Incompatible example: HSTL_IV_DCI input and HSTL_III_DCI input
b.
No more than one Split Termination type (input or output) is allowed in the same bank.
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QPro Virtex-II 1.5V Military QML Platform FPGAs The implementation tools will enforce these design rules.
Incompatible example: HSTL_I_DCI input and HSTL_II_DCI input
Table 10 summarizes all standards and voltage supplies. Table 10: Summary of Voltage Supply Requirements for All Input and Output Standards
VCCO I/O Standard LVDS_33 LVDSEXT_33 LVPECL_33 N/R SSTL3_I SSTL3_II AGP LVTTL LVCMOS33 LVDCI_33 LVDCI_DV2_33 PCI33_3 PCI66_3 PCIX LVDS_33_DCI LVDSEXT_33_DCI SSTL3_I_DCI SSTL3_II_DCI LVDS_25 LVDSEXT_25 LDT_25 ULVDS_25 BLVDS_25 SSTL2_I SSTL2_II 2.5 LVCMOS25 LVDCI_25 LVDCI_DV2_25 LVDS_25_DCI LVDSEXT_25_DCI SSTL2_I_DCI SSTL2_II_DCI 2.5 N/R N/R N/R N/R N/R 1.25 1.25 N/R Series Series N/R N/R N/R Split N/R N/R N/R Split Split Split Split N/R 3.3 3.3 1.5 1.5 1.32 N/R N/R N/R N/R N/R N/R N/R N/R N/R 1.5 1.5 N/R N/R N/R N/R N/R 1.25 1.25 N/R N/R N/R N/R N/R Series Series N/R N/R N/R N/R N/R N/R Split N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R Split Split Split Split N/R N/R N/R N/R N/R N/R N/R Output Input VREF Input N/R (1) N/R N/R Termination Type Output N/R N/R N/R Input N/R N/R N/R I/O Standard HSTL_III_18 HSTL_IV_18 HSTL_I_18 N/R HSTL_II_18 SSTL18_I SSTL18_II LVCMOS18 LVDCI_18 LVDCI_DV2_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 HSTL_I_DCI_18 HSTL_II_DCI_18 SSTL18_I_DCI SSTL18_II_DCI HSTL_III HSTL_IV N/R HSTL_I HSTL_II LVCMOS15 LVDCI_15 1.5 LVDCI_DV2_15 GTLP_DCI 1.5 HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI HSTL_II_DCI GTL_DCI GTLP N/R GTL Notes: 1. N/R = no requirement. N/R 0.8 N/R N/R 1.2 1.2 0.9 0.9 0.75 0.75 0.8 1 N/R Single N/R Split Single N/R Single Single Split Split Single N/R N/R 1 Series Single N/R Single 0.75 0.75 N/R N/R N/R N/R N/R Series N/R N/R N/R N/R 1.8 1.8 0.9 0.9 0.9 N/R N/R N/R 1.1 1.1 0.9 0.9 0.9 0.9 0.9 0.9 N/R N/R N/R N/R Series Series N/R Single N/R Split N/R Split N/R N/R N/R N/R N/R N/R N/R N/R Single Single Split Split Split Split N/R N/R
Table 10: Summary of Voltage Supply Requirements for All Input and Output Standards (Continued)
VCCO Output Input VREF Input 1.1 1.1 0.9 Termination Type Output N/R N/R N/R Input N/R N/R N/R
Digitally Controlled Impedance (DCI)
Today's chip output signals with fast edge rates require termination to prevent reflections and maintain signal integrity.
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QPro Virtex-II 1.5V Military QML Platform FPGAs High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Virtex-II XCITE DCI provides controlled impedance drivers and on-chip termination for single-ended and differential I/Os. This eliminates the need for external resistors, and improves signal integrity. The DCI feature can be used on any IOB by selecting one of the DCI I/O standards. When applied to inputs, DCI provides input parallel termination. When applied to outputs, DCI provides controlled impedance drivers (series termination) or output parallel termination. DCI operates independently on each I/O bank. When a DCI I/O standard is used in a particular I/O bank, external reference resistors must be connected to two dual-function pins on the bank. These resistors, the voltage reference of the N transistor (VRN), and the voltage reference of the P transistor (VRP) are shown in Figure 10.
1 Bank DCI DCI
R
Controlled Impedance Drivers (Series Termination)
DCI can be used to provide a buffer with a controlled output impedance. It is desirable for this output impedance to match the transmission line impedance (Z). Virtex-II input buffers also support LVDCI and LVDCI_DV2 I/O standards.
IOB Z Z
Virtex-II DCI VCCO = 3.3 V, 2.5 V, 1.8 V or 1.5 V
DS031_51_110600
Figure 11: Internal Series Termination Table 11: SelectI/O-Ultra Controlled Impedance Buffers VCCO 3.3 V 2.5 V 1.8 V 1.5 V DCI LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 DCI Half Impedance LVDCI_DV2_33 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15
DCI DCI VCCO RREF (1%) VRN VRP RREF (1%) GND
DS031_50_101200
Controlled Impedance Drivers (Parallel Termination)
DCI also provides on-chip termination for SSTL3, SSTL2, HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or transmitters on bidirectional lines. Table 12 lists the on-chip parallel terminations available in Virtex-II devices. VCCO must be set according to Table 8. Note that there is a VCCO requirement for GTL_DCI and GTLP_DCI, due to the on-chip termination resistor. Table 12: SelectI/O-Ultra Buffers with On-Chip Parallel Termination I/O Standard SSTL3 Class I SSTL3 Class II SSTL2 Class I SSTL2 Class II HSTL Class I HSTL Class II HSTL Class III HSTL Class IV External Termination SSTL3_I SSTL3_II SSTL2_I SSTL2_II HSTL_I HSTL_II HSTL_III HSTL_IV On-Chip Termination SSTL3_I_DCI (1) SSTL3_II_DCI (1) SSTL2_I_DCI (1) SSTL2_II_DCI (1) HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI
Figure 10: DCI in a Virtex-II Bank When used with a terminated I/O standard, the value of resistors are specified by the standard (typically 50 ). When used with a controlled impedance driver, the resistors set the output impedance of the driver within the specified range (25 to 100 ) . For all series and parallel terminations listed in Table 11 and Table 12, the reference resistors must have the same value for any given bank. One percent resistors are recommended. The DCI system adjusts the I/O impedance to match the two external reference resistors or half of the reference resistors, and compensates for impedance changes due to voltage and/or temperature fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off.
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QPro Virtex-II 1.5V Military QML Platform FPGAs Figure 12 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the Virtex-II User Guide (UG002).
Table 12: SelectI/O-Ultra Buffers with On-Chip Parallel Termination (Continued) I/O Standard GTL GTLP
Notes: 1. SSTL Compatible
External Termination GTL GTLP
On-Chip Termination GTL_DCI GTLP_DCI
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
VCCO/2
VCCO/2 R Z0
VCCO/2 R Z0
VCCO R
VCCO R Z0
VCCO R
Conventional
R Z0
DCI Transmit Conventional Receive
Virtex-II DCI
VCCO/2 R Z0
VCCO 2R Z0 2R Virtex-II DCI
VCCO/2 R Z0 Virtex-II DCI
VCCO R
VCCO R Z0 Virtex-II DCI
VCCO R
VCCO
VCCO/2 R Z0
VCCO 2R Z0 Virtex-II DCI VCCO R 2R Virtex-II DCI VCCO R Z0 Virtex-II DCI VCCO R
Conventional Transmit DCI Receive
2R Z0 2R Virtex-II DCI
VCCO
VCCO 2R Z0 2R Virtex-II DCI
DCI Transmit DCI Receive
Virtex-II DCI
2R Z0 2R Virtex-II DCI
VCCO 2R Z0 Virtex-II DCI
VCCO R
VCCO R Z0
VCCO R
2R Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
VCCO 2R
VCCO 2R Z0 2R
VCCO R
VCCO R Z0
Bidirectional
N/A
2R
N/A
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Reference Resistor
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
DS031_65a_100201
Recommended Z0
Figure 12: HSTL DCI Usage Examples
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QPro Virtex-II 1.5V Military QML Platform FPGAs
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Figure 13 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O standards. For a complete list, see the Virtex-II User Guide (UG002).
SSTL2_I
VCCO/2 R VCCO/2 R VCCO/2 R Z0 R/2 Z0 R/2
SSTL2_II
SSTL3_I
SSTL3_II
VCCO/2 R VCCO/2 R Z0 VCCO/2 R
Conventional
R/2
Z0 R/2
VCCO/2
DCI Transmit Conventional Receive
VCCO 25(1) 2R Z0 2R
VCCO/2 R 25(1) Z0 Virtex-II DCI
25(1) Z0 Virtex-II DCI
VCCO/2 R
R
25(1)
VCCO 2R Z0 2R
VCCO/2 R
Virtex-II DCI
Virtex-II DCI
VCCO
VCCO/2 R Z0 R/2
VCCO 2R Z0 2R Virtex-II DCI R/2
VCCO 2R
VCCO/2 R Z0 R/2
VCCO 2R
Conventional Transmit DCI Receive
2R Z0 R/2 2R Virtex-II DCI
2R Virtex-II DCI
2R Virtex-II DCI
VCCO 25(1) 2R Z0 2R Virtex-II DCI Virtex-II DCI
25(1)
VCCO 2R Z0 2R
VCCO 2R 25(1) Z0 2R Virtex-II DCI Virtex-II DCI
VCCO 2R
DCI Transmit DCI Receive
VCCO 25(1) 2R Z0 2R Virtex-II DCI
VCCO 2R
2R Virtex-II DCI
2R Virtex-II DCI
Virtex-II DCI
VCCO 25(1) 2R
VCCO 2R Z0 2R
25(1)
VCCO 2R Z0 2R
VCCO 2R 2R
Bidirectional
N/A
2R
25(1)
N/A
25(1)
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Reference Resistor
VRN = VRP = R = Z0 50
Notes:
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
Recommended Z0(2)
1. The SSTL-compatible 25 series resistor is accounted for in the DCI buffer, and it is not DCI controlled. 2. Z0 is the recommended PCB trace impedance.
DS031_65b_112502
Figure 13: SSTL DCI Usage Examples
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QPro Virtex-II 1.5V Military QML Platform FPGAs
Figure 14 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list, see the Virtex-II User Guide (UG002).
LVDS_DCI and LVDSEXT_DCI Receiver
Z0
Conventional
2R
Z0
Virtex-II LVDS
VCCO 2R
Z0
2R Conventional Transmit DCI Receive
Z0
VCCO 2R 2R Virtex-II LVDS DCI
Reference Resistor Recommended Z0
VRN = VRP = R = Z0 50
DS031_65c_082102
Figure 14: LVDS DCI Usage Examples
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Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing matrix, as shown in Figure 15. A CLB element comprises four similar slices with fast local feedback within the CLB. The four slices are split into two columns of two slices with two independent carry logic chains and one common shift chain.
TBUF X0Y1 TBUF X0Y0 COUT Slice X1Y1 Slice X1Y0 SHIFT Slice X0Y1 Slice X0Y0 CIN CIN Fast Connects to neighbors
DS031_32_101600
Configurations
Look-Up Table Virtex-II function generators are implemented as 4-input look-up tables (LUTs). Four independent inputs are provided to each of the two function generators in a slice (F and G). These function generators are each capable of implementing any arbitrarily defined Boolean function of four inputs. The propagation delay is therefore independent of the function implemented. Signals from the function generators can exit the slice (X or Y output), can input the XOR dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the D input of the storage element, or go to the MUXF5 (not shown in Figure 17). In addition to the basic LUTs, the Virtex-II slice contains logic (MUXF5 and MUXFX multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. The MUXFXs are either MUXF6, MUXF7, or MUXF8 according to the slice considered in the CLB. Selected functions up to nine inputs (MUXF5 multiplexer) can be implemented in one slice. The MUXFX can also be a MUXF6, MUXF7, or MUXF8 multiplexer to map any functions of six, seven, or eight inputs and selected wide logic functions. Register/Latch The storage elements in a Virtex-II slice can be configured as either edge-triggered D-type flip-flops or level-sensitive latches. The D input can be directly driven by the X or Y output via the DX or DY input, or by the slice inputs bypassing the function generators via the BX or BY input. The clock enable signal (CE) is active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR and BY slice inputs). SR forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic "1" when SR is asserted. SRLOW forces a logic "0". When SR is used, a second input (BY) forces the storage element into the opposite state. The reset condition is predominant over the set condition. (See Figure 18.) The initial state after configuration or global initial state is defined by a separate INIT0 and INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. For each slice, set and reset can be set to be synchronous or asynchronous. Virtex-II devices also have the ability to set INIT0 and INIT1 independent of SRHIGH and SRLOW. Control signals CLK, CE, and SR are common to both storage elements in one slice. All control signals have independent polarities. Any inverter placed on a control input is automatically absorbed.
DS122 (v1.1) January 7, 2004 Product Specification
Switch Matrix
COUT
Figure 15: Virtex-II CLB Element
Slice Description
Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. As shown in Figure 16, each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable-tap shift register element.
RAM16
ORCY MUXFx
SRL16 LUT G RAM16 MUXF5 SRL16 LUT F CY Register CY Register
Arithmetic Logic
DS031_31_100900
Figure 16: Virtex-II Slice Configuration The output from the function generator in each slice drives both the slice output and the D input of the storage element. Figure 17 shows a more detailed view of a single slice.
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QPro Virtex-II 1.5V Military QML Platform FPGAs
SHIFTIN
COUT
SOPIN 0 Dual-Port Shift-Reg G4 G3 G2 G1 WG4 WG3 WG2 WG1 ALTDIG MULTAND 1 0 BY SLICEWE[2:0] G2 PROD G1 CYOG BY A4 LUT A3 RAM A2 ROM A1 D WG4 G WG3 WG2 MC15 WG1 WS DI
ORCY SOPOUT
YBMUX 1 MUXCY 1 0
YB
GYMUX
Y DY
XORG FF LATCH DYMUX CE CLK D Y Q
Q
CE CK SR REV
WSG WE[2:0] WE CLK WSF
SHIFTOUT
SR DIG MUXCY 1 0
CE CLK SR CIN
DS031_01_112502
Shared between x & y Registers
Figure 17: Virtex-II Slice (Top Half)
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QPro Virtex-II 1.5V Military QML Platform FPGAs * * *
YQ Attribute INIT1 INIT0 SRHIGH SRLOW
R
FFY FF LATCH DY D Q
Dual-Port 16 x 4 bit RAM Dual-Port 32 x 2 bit RAM Dual-Port 64 x 1 bit RAM
CE CK SR REV BY FFX FF LATCH DX CE CLK SR BX D CE CK SR REV Q
Distributed SelectRAM memory modules are synchronous (write) resources. The combinatorial read access time is extremely fast, while the synchronous write simplifies high-speed designs. A synchronous read can be implemented with a storage element in the same slice. The distributed SelectRAM memory and the storage element share the same clock input. A Write Enable (WE) input is active High, and is driven by the SR input. Table 13 shows the number of LUTs (2 per slice) occupied by each distributed SelectRAM configuration. Table 13: Distributed SelectRAM Configurations RAM 16 x 1S 16 x 1D 32 x 1S 32 x 1D 64 x 1S 64 x 1D Number of LUTs 1 2 2 4 4 8 8
XQ Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC
DS031_22_110600
Figure 18: Register/Latch Configuration in a Slice The set and reset functionality of a register or a latch can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear)
128 x 1S
Notes: 1. S = single-port configuration, and D = dual-port configuration.
For single-port configurations, distributed SelectRAM memory has one address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed SelectRAM memory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. The function generator (LUT) has separated read address inputs (A1, A2, A3, A4) and write address inputs (WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4). In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator (R/W port) is connected with shared read and write addresses. The second function generator has the A inputs (read) connected to the second read-only port address and the W inputs (write) shared with the first read/write port address.
The synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. Distributed SelectRAM Memory Each function generator (LUT) can implement a 16 x 1-bit synchronous RAM resource called a distributed SelectRAM element. The SelectRAM elements are configurable within a CLB to implement the following: * * * * Single-Port 16 x 8 bit RAM Single-Port 32 x 4 bit RAM Single-Port 64 x 2 bit RAM Single-Port 128 x 1 bit RAM
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Figure 19, Figure 20, and Figure 21 illustrate various example configurations.
RAM 16x1S DPRA[3:0] D D DI (optional) Q Output Registered Output A[3:0] 4 4
RAM 16x1D
A[3:0]
4 4 (BY)
RAM A[4:1] WG[4:1] WS
dual_port RAM G[4:1] D WG[4:1] WS DI
DPO
D
(BY) WSG WE CK
D
WSG WE WCLK (SR) WE CK
DS031_02_110303
Figure 19: Distributed SelectRAM (RAM16x1S)
A[3:0]
4
dual_port RAM G[4:1] D WG[4:1] WS DI
SPO
RAM 32x1S A[4] A[3:0] (BX) 4 RAM G[4:1] WG[4:1] WS D (BY) WSG WE0 WE CK WSF WS DI RAM D F[4:1] WF[4:1] DI
DS031_04_110100
WSG WE WCLK (SR) WE CK
D
WE WCLK
(SR)
Output F5MUX DQ Registered Output
Figure 21: Dual-Port Distributed SelectRAM (RAM16x1D) Similar to the RAM configuration, each function generator (LUT) can implement a 16 x 1-bit ROM. Five configurations are available: ROM16x1, ROM32x1, ROM64x1, ROM128x1, and ROM256x1. The ROM elements are cascadable to implement wider or/and deeper ROM. ROM contents are loaded at configuration. Table 14 shows the number of LUTs occupied by each configuration. Table 14: ROM Configuration ROM 16 x 1 32 x 1 64 x 1 128 x 1 256 x 1 Number of LUTs 1 2 4 8 (1 CLB) 16 (2 CLBs)
4
(optional)
DS031_03_110100
Figure 20: Single-Port Distributed SelectRAM (RAM32x1S)
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Shift Registers Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 22. A dynamic read access is performed through the 4-bit address bus, A[3:0]. The configurable 16-bit shift register cannot be set or reset. The read is asynchronous, however, the storage element or flip-flop is available to implement a synchronous read. The storage element should always be used with a constant address. For example, when building an 8-bit shift register and configuring the addresses to point to the seventh bit, the eighth bit can be the flip-flop. The overall system performance is improved by using the superior clock-to-out of the flip-flops.
SHIFTIN SRLC16 1 Shift Chain in CLB IN
DI D SRLC16 MC15
FF
DI D SRLC16 MC15 SLICE S3
FF
SHIFTOUT
SHIFTIN DI D SRLC16 MC15 FF
SHIFT-REG A[3:0] 4 A[4:1] D MC15 D WS D(BY) WSG CE (SR) CLK WE CK (optional) SHIFTIN DI D SRLC16 MC15
DS031_05_110600
Output Q Registered Output
DI
SLICE S2
DI D SRLC16 MC15
FF
SHIFTOUT
FF
SHIFTOUT
Figure 22: Shift Register Configurations An additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary LUT output. (See Figure 23.) Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the MUXF5, MUXF6, and MUXF7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one CLB.
DI D SRLC16 MC15 FF SLICE S1 SHIFTOUT
SHIFTIN DI D SRLC16 MC15 FF
DI D SRLC16 MC15
FF SLICE S0 OUT CASCADABLE OUT
DS031_06_110200
CLB
Figure 23: Cascadable Shift Register
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QPro Virtex-II 1.5V Military QML Platform FPGAs Each Virtex-II slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 24. Each CLB element has two MUXF6 multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. Examples of multiplexers are shown in the Virtex-II User Guide (UG002). Any LUT can implement a 2:1 multiplexer.
Multiplexers Virtex-II function generators and associated multiplexers can implement the following: * * * * 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one CLB element (4 slices) 32:1 multiplexer in two CLB elements (8 slices)
F8
Slice S3
G F F5
MUXF8 combines the two MUXF7 outputs (Two CLBs)
F6
F
F7
F5
Slice S2
G
MUXF6 combines the two MUXF5 outputs from slices S2 and S3
G F F5
Slice S1
MUXF7 combines the two MUXF6 outputs from slices S0 and S2
F6
G F F5
Slice S0
MUXF6 combines the two MUXF5 outputs from slices S0 and S1
CLB
DS031_08_100201
Figure 24: MUXF5 and MUXFX multiplexers Fast Lookahead Carry Logic Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II CLB has two separate carry chains, as shown in the Figure 25. The height of the carry chains is two bits per slice. The carry chain in the Virtex-II device is running upward. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. Arithmetic Logic The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, a dedicated AND (MULT_AND) gate (shown in Figure 17) improves the efficiency of multiplier implementation.
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COUT to S0 of the next CLB
COUT to CIN of S2 of the next CLB
OI LUT (First Carry Chain)
MUXCY FF
SLICE S3 OI LUT MUXCY FF
CIN COUT OI LUT MUXCY FF
SLICE S2 OI OI LUT MUXCY FF LUT MUXCY FF
OI LUT
MUXCY FF
SLICE S1
CIN COUT OI LUT MUXCY FF
(Second Carry Chain)
OI LUT
MUXCY FF
SLICE S0
CIN
CIN
CLB
DS031_07_110200
Figure 25: Fast Carry Logic Path
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Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are designed for implementing large, flexible SOP chains. One input of each ORCY is connected through the fast SOP chain to the output of the previous ORCY in the same slice row. The second input is connected to the output of the top MUXCY in the same slice, as shown in Figure 26. LUTs and MUXCYs can implement large AND gates or other combinatorial logic functions. Figure 27 illustrates LUT and MUXCY resources configured as a 16-input AND gate.
ORCY 4 4
ORCY 4
ORCY 4
ORCY SOP
LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
Slice 1 4 LUT
MUXCY
Slice 3 4 LUT
MUXCY
Slice 1 4 LUT
MUXCY
Slice 3 4 LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
Slice 0 4 LUT
MUXCY
Slice 2 4 LUT
MUXCY
Slice 0 4 LUT
MUXCY
Slice 2 4 LUT
MUXCY
VCC
VCC CLB
VCC
VCC CLB
ds031_64_110300
Figure 26: Horizontal Cascade Chain
OUT
4 LUT
MUXCY 0 1 "0" Slice
4 LUT
MUXCY 0 1 "0" 16 AND OUT
4 LUT
MUXCY 0 1 "0" Slice
4 LUT
MUXCY 0 1 VCC
DS031_41_110600
Figure 27: Wide-Input AND Gate (16 Inputs)
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3-State Buffers
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs) that can drive on-chip buses. Each 3-state buffer has its own 3-state control pin and its own input pin. Each of the four slices have access to the two 3-state buffers through the switch matrix, as shown in Figure 28. TBUFs in neighboring CLBs can access slice outputs by direct connects. The outputs of the 3-state buffers drive horizontal routing resources used to implement 3-state buses.
The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that timing is more predictable and less load dependent especially with larger devices.
Locations/Organization
Four horizontal routing resources per CLB are provided for on-chip 3-state buses. Each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in Figure 29. The switch matrices corresponding to SelectRAM memory and multiplier or I/O blocks are skipped.
Number of 3-State Buffers
TBUF
TBUF
Slice S3 Slice S2
Table 15 shows the number of 3-state buffers available in each Virtex-II device. The number of 3-state buffers is twice the number of CLB elements. Table 15: Virtex-II 3-State Buffers Device XQ2V1000 XQ2V3000 XQ2V6000 3-State Buffers per Row 64 112 176 Total Number of 3-State Buffers 2,560 7,168 16,896
Switch Matrix Slice S1 Slice S0
DS031_37_060700
Figure 28: Virtex-II 3-State Buffers
3 - state lines
Switch matrix CLB-II
Programmable connection
Switch matrix CLB-II
DS031_09_032700
Figure 29: 3-State Buffer Connection to Horizontal Lines
CLB/Slice Configurations
Table 16 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be impleTable 16: Logic Resources in One CLB Slices 4 LUTs 8 Flip-Flops 8 MULT_ANDs 8
mented in one of the configurations listed. Table 17 shows the available resources in all CLBs.
Arithmetic & Carry Chains 2
SOP Chains 2
Distributed SelectRAM 128 bits
Shift Registers 128 bits
TBUF 2
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QPro Virtex-II 1.5V Military QML Platform FPGAs
Table 17: Virtex-II Logic Resources Available in All CLBs CLB Array: Row x Column 40 x 32 64 x 56 96 x 88 Number of Slices 5,120 14,336 33,792 Number of LUTs 10,240 28,672 67,584 Max Distributed SelectRAM or Shift Register (bits) 163,840 458,752 1,081,344 Number of Flip-Flops 10,240 28,672 67,584 Number of Carry Chains (1) 64 112 176 Number of SOP Chains (1) 80 128 192
Device XQ2V1000 XQ2V3000 XQ2V6000
Notes: 1. The carry chains and SOP chains can be split or cascaded.
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures implemented in CLBs. Each Virtex-II block SelectRAM is an 18 Kbit true dual-port RAM with two independently clocked and independently controlled synchronous ports that access a common storage area. Both ports are functionally identical. CLK, EN, WE, and SSR polarities are defined through configuration. Each port has the following types of inputs: Clock and Clock Enable, Write Enable, Set/Reset, and Address, as well as separate Data/parity data inputs (for writes) and Data/parity data outputs (for reads). Operation is synchronous. The block SelectRAM behaves like a register. Control, address, and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. Data outputs change as a result of the same clock edge. 1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit memory locations in any of the 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations. The advantage of 9-bit, 18-bit, and 36-bit widths is the ability to store a parity bit for every eight bits. Parity bits must be generated or checked externally in user logic. In such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored and behave exactly as the other bits, including the timing parameters. Video applications can use the 9-bit ratio of Virtex-II block SelectRAM memory to advantage. Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 30. Input data bus and output data bus widths are identical.
18 Kbit Block SelectRAM DI DIP ADDR WE EN SSR CLK
Configuration
The Virtex-II block SelectRAM supports various configurations, including single- and dual-port RAM and various data/address aspect ratios. Supported memory configurations for single- and dual-port modes are shown in Table 18. Table 18: Dual- and Single-Port Configurations 16K x 1 bit 8K x 2 bits 4K x 4 bits 2K x 9 bits 1K x 18 bits 512 x 36 bits
DO DOP
DS031_10_071602
Figure 30: 18 Kbit Block SelectRAM Memory in Single-Port Mode
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has access to a common 18 Kbit memory resource. These are fully synchronous ports with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion.
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to the 18 Kbit memory locations in any of the 2K x 9-bit,
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 19 illustrates the different configurations available on Ports A and B. Table 19: Dual-Port Mode Configurations Port A Port B Port A Port B Port A Port B Port A Port B Port A Port B Port A Port B 16K x 1 16K x 1 8K x 2 8K x 2 4K x 4 4K x 4 2K x 9 2K x 9 1K x 18 1K x 18 512 x 36 512 x 36 16K x 1 8K x 2 8K x 2 4K x 4 4K x 4 2K x 9 2K x 9 1K x 18 1K x 18 512 x 36 16K x 1 4K x 4 8K x 2 2K x 9 4K x 4 1K x 18 2K x 9 512 x 36 16K x 1 2K x 9 8K x 2 1K x 18 4K x 4 512 x 36 16K x 1 1K x 18 8K x 2 512 x 36 16K x 1 512 x 36
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If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18 Kbit block is accessible from Port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations, the 16 Kbit block is accessible from Port A or Port B. All other configurations result in one port having access to an 18 Kbit memory block and the other port having access to a 16 Kbit subset of the memory block equal to 16 Kbits. Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 31. The two ports have independent inputs and outputs and are independently clocked.
18 Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA
Port Aspect Ratios
Table 20 shows the depth and the width aspect ratios for the 18 Kbit block SelectRAM. Virtex-II block SelectRAM also includes dedicated routing resources to provide an efficient interface with CLBs, block SelectRAM, and multipliers. Table 20: 18 Kbit Block SelectRAM Port Aspect Ratio
Width 1 2 4 9 18 36 Depth 16,384 8,192 4,096 2,048 1,024 512 Address Bus ADDR[13:0] ADDR[12:0] ADDR[11:0] ADDR[10:0] ADDR[9:0] ADDR[8:0] Data Bus DATA[0] DATA[1:0] DATA[3:0] DATA[7:0] DATA[15:0] DATA[31:0] Parity Bus N/A N/A N/A Parity[0] Parity[1:0] Parity[3:0]
DOA DOPA
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully synchronous. An address is presented, and the read operation is enabled by control signals WEA and WEB in addition to ENA or ENB. Then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into output registers.
DIB DIPB ADDRB WEB ENB SSRB CLKB
DOB DOPB
DS031_11_071602
Figure 31: 18 Kbit Block SelectRAM in Dual-Port Mode
The write operation is also fully synchronous. Data and address are presented, and the write operation is enabled by control signals WEA or WEB in addition to ENA or ENB. Then, again depending on the clock input mode, a rising or falling clock edge causes the data to be loaded into the memory cell addressed.
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QPro Virtex-II 1.5V Military QML Platform FPGAs memory also transfers the prior content of the memory cell addressed into the data output registers DO, as shown in Figure 33. 3. "NO_CHANGE" The "NO_CHANGE" option maintains the content of the output registers, regardless of the write operation. The clock edge during the write mode has no effect on the content of the data output register DO. When the port is configured as "NO_CHANGE", only a read operation loads a new value in the output register DO, as shown in Figure 34.
A write operation performs a simultaneous read operation. Three different options are available, selected by configuration: 1. "WRITE_FIRST" The "WRITE_FIRST" option is a transparent mode. The same clock edge that writes the data input (DI) into the memory also transfers DI into the output registers DO as shown in Figure 32. 2. "READ_FIRST" The "READ_FIRST" option is a read-before-write mode. The same clock edge that writes data input (DI) into the
Internal Memory
Data_in
DI
DO
Data_out = Data_in
CLK WE Data_in Address RAM Contents Data_out New aa Old New New
DS031_14_102000
Figure 32: WRITE_FIRST Mode
Data_in
DI
Internal Memory
DO
Prior stored data
CLK WE Data_in Address RAM Contents Data_out New aa Old New Old
DS031_13_102000
Figure 33: READ_FIRST Mode
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Data_in
DI
Internal Memory
DO
No change during write
CLK WE Data_in Address RAM Contents Data_out New aa Old New Last Read Cycle Content (no change)
DS031_12_102000
Figure 34: NO_CHANGE Mode
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports with the control signals described in Table 21. All control inputs including the clock have an optional inversion. Table 21: Control Functions Control Signal CLK EN WE SSR Function Read and Write Clock Enable affects Read, Write, Set, Reset Write Enable Set DO register to SRVAL (attribute)
for each port when a block SelectRAM resource is configured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either four or six columns. The number of blocks per column depends of the device array size and is equivalent to the number of CLBs in a column divided by four. Column locations are shown in Table 22. Table 22: SelectRAM Memory Floor Plan SelectRAM Blocks Device XQ2V1000 Columns 4 6 6 Per Column 10 16 24 Total 40 96 144
Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the output register value after device configuration (INIT) and SSR is asserted (SRVAL). Both attributes (INIT_B and SRVAL) are available
XQ2V3000 XQ2V6000
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SelectRAM Blocks
SelectRAM Blocks
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
2 CLB columns
2 CLB columns
SelectRAM Blocks
n CLB columns
n CLB columns
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
ds031_38_110403
Figure 35: Block SelectRAM (2-column, 4-column, and 6-column)
Total Amount of SelectRAM Memory
Table 23 shows the amount of block SelectRAM memory available for each Virtex-II device. The 18 Kbit SelectRAM blocks are cascadable to implement deeper or wider single- or dual-port memory resources. Table 23: Virtex-II SelectRAM Memory Available Total SelectRAM Memory Device XQ2V1000 XQ2V3000 XQ2V6000 Blocks 40 96 144 in Kbits 720 1,728 2,592 in Bits 737,280 1,769,472 2,654,208
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II multiplier block is an 18-bit by 18-bit 2's complement signed multiplier. Virtex-II devices incorporate many embedded multiplier blocks. These multipliers can be associated with an 18 Kbit block SelectRAM resource or can be used independently. They are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. Each SelectRAM memory and multiplier block is tied to four switch matrices, as shown in Figure 36.
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2 CLB columns
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Configuration
Switch Matrix
The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-bit-wide inputs, and the output is 36 bits. Figure 37 shows a multiplier block.
18 x 18 Multiplier Multiplier Block A[17:0]
Switch Matrix 18-Kbit block SelectRAM Switch Matrix
MULT 18 x 18 B[17:0]
P[35:0]
Switch Matrix
DS031_40_100400
Figure 37: Multiplier Block
DS031_33_101000
Figure 36: SelectRAM and Multiplier Blocks
Locations/Organization
Multiplier organization is identical to the 18 Kbit SelectRAM organization, because each multiplier is associated with an 18 Kbit block SelectRAM resource. In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs)). Table 24: Multiplier Floor Plan Multipliers Device XQ2V1000 XQ2V3000 XQ2V6000 Columns 4 6 6 Per Column 10 16 24 Total 40 96 144
Association with Block SelectRAM Memory
The interconnect is designed to allow SelectRAM memory and multiplier blocks to be used at the same time, but some interconnect is shared between the SelectRAM and the multiplier. Thus, SelectRAM memory can be used only up to 18 bits wide when the multiplier is used, because the multiplier shares inputs with the upper data bits of the SelectRAM memory. This sharing of the interconnect is optimized for an 18-bit-wide block SelectRAM resource feeding the multiplier. The use of SelectRAM memory and the multiplier with an accumulator in LUTs allows for implementation of a digital signal processor (DSP) multiplier-accumulator (MAC) function, which is commonly used in finite and infinite impulse response (FIR and IIR) digital filters.
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Multiplier Blocks
Multiplier Blocks
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
2 CLB columns
2 CLB columns
Multiplier Blocks
n CLB columns
n CLB columns
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
DS031_39_110403
Figure 38: Multipliers (2-column, 4-column, and 6-column)
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads are on the top edge of the device, in the middle of the array, and eight are on the bottom edge, as illustrated in Figure 39. The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in Virtex-II devices. Like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge.
8 clock pads
Virtex-II Device
8 clock pads
2 CLB columns
2 CLB columns
DS031_42_101000
Figure 39: Virtex-II Clock Pads
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QPro Virtex-II 1.5V Military QML Platform FPGAs Each global clock buffer can be driven by either the clock pad to distribute a clock directly to the device, or the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 36. Each global clock buffer can also be driven by local interconnects. The DCM has clock output(s) that can be connected to global clock buffer inputs, as shown in Figure 40.
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bution detail of the device prior to pin-locking and floorplanning (see the Virtex-II User Guide, UG002). Figure 42 shows clock distribution in Virtex-II devices. In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight down). For the largest devices a new clock row is added, as necessary. To reduce power consumption, any unused clock branches remain static. Global clocks are driven by dedicated clock buffers (BUFG), which can also be used to gate the clock (BUFGCE) or to multiplex between two independent clock inputs (BUFGMUX). The most common configuration option of this element is as a buffer. A BUFG function in this (global buffer) mode, is shown in Figure 41.
Clock Pad I Clock Buffer
Clock Pad
CLKIN
DCM
CLKOUT
0 Clock Distribution
I Clock Buffer
BUFG I O
DS031_61_101200
0 Clock Distribution
DS031_43_101000
Figure 41: Virtex-II BUFG Function The Virtex-II global clock buffer BUFG can also be configured as a clock enable/disable circuit (Figure 43), as well as a two-input clock multiplexer (Figure 44). A functional description of these two options is provided below. Each of them can be used in either of two modes, selected by configuration: rising clock edge or falling clock edge.
Figure 40: Virtex-II Clock Distribution Configurations Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in CLBs and IOBs, and SelectRAM blocks). Eight global clocks can be used in each quadrant of the Virtex-II device. Designers should consider the clock distri-
8 BUFGMUX
NW
NE
8
NW
8 BUFGMUX
NE
8
8 max
16 Clocks
8
16 Clocks
8
SW
8 BUFGMUX
SE
SW
SE
8 BUFGMUX
DS031_45_120200
Figure 42: Virtex-II Clock Distribution
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QPro Virtex-II 1.5V Military QML Platform FPGAs If the presently selected clock is Low while S changes, or if it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transition from High to Low. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock, that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. All Virtex-II devices have 16 global clock multiplexer buffers. Figure 45 shows a switchover from CLK0 to CLK1.
Wait for Low
This section describes the rising clock edge option. For the opposite option, falling clock edge, just change all "rising" references to "falling" and all "High" references to "Low", except for the description of the CE or S levels. The rising clock edge option uses the BUFGCE and BUFGMUX primitives. The falling clock edge option uses the BUFGCE_1 and BUFGMUX_1 primitives.
BUFGCE
If the CE input is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming clock High time has no effect.
BUFGCE I CE O
S
DS031_62_101200
Figure 43: Virtex-II BUFGCE Function If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output.
CLK0 Switch CLK1 OUT
DS031_46_112900
Figure 45: Clock Multiplexer Waveform Diagram In Figure 45: * * * * * * The current clock is CLK0. S is activated High. If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. When CLK1 transitions from High to Low, the output switches to CLK1. No glitches or short pulses can appear on the output.
BUFGMUX
BUFGMUX can switch between two unrelated, even asynchronous clocks. Basically, a Low on S selects the I0 input, and a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and Low time is never shorter than the shortest High or Low time of either input clock. As long as the presently selected clock is High, any level change of S has no effect.
BUFGMUX I0 I1 S
DS031_63_112900
O
Figure 44: Virtex-II BUFGMUX Function
Local Clocking
In addition to global clocks, there are local clock resources in the Virtex-II devices. There are more than 72 local clocks in the Virtex-II family. These resources can be used for many different applications, including but not limited to memory interfaces. For example, even using only the left and right I/O banks, Virtex-II FPGAs can support up to 50 local clocks for DDR SDRAM. These interfaces can operate beyond 200 MHz on Virtex-II devices.
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Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock management features: * Clock De-skew: The DCM generates new system clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, thus eliminating clock distribution delays. Frequency Synthesis: The DCM generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. Phase Shifting: The DCM provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. Table 25: DCM Status Pins Status Pin 0 1 2 3 4 5 6 7 Function Phase Shift Overflow CLKIN Stopped CLKFX Stopped N/A N/A N/A N/A N/A
*
*
The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. It also utilizes fully digital feedback systems, operating dynamically to compensate for temperature and voltage variations during operation. Up to four of the nine DCM clock outputs can drive inputs to global clock buffers or global clock multiplexer buffers simultaneously (see Figure 46). All DCM clock outputs can simultaneously drive general routing resources, including routes to output buffers.
Clock De-Skew
The DCM de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. Additional delay is introduced so that clock edges arrive at internal registers and block RAMs simultaneously with the clock edges arriving at the input clock pad. Alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. All DCM output clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. To achieve clock de-skew, the CLKFB input must be connected, and its source must be either CLK0 or CLK2X. CLKFB must always be connected, unless only the CLKFX or CLKFX180 outputs are used and de-skew is not required.
DCM
CLKIN CLKFB RST DSSEN CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV
Frequency Synthesis
The DCM provides flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output creates divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The CLKFX and CLKFX180 outputs can be used to produce clocks at the following frequency: FREQCLKFX = (M/D) * FREQCLKIN where M and D are two integers. Specifications for M and D are provided under DCM Timing Parameters. By default, M=4 and D=1, which results in a clock output frequency four times faster than the clock input frequency (CLKIN). CLK2X180 is phase shifted 180 degrees relative to CLK2X. CLKFX180 is phase shifted 180 degrees relative to CLKFX. All frequency synthesis outputs automatically have 50/50 duty cycles (with the exception of the CLKDV output when performing a non-integer divide in high-frequency mode). Note that CLK2X and CLK2X180 are not available in high-frequency mode.
DS122 (v1.1) January 7, 2004 Product Specification
PSINCDEC CLKFX PSEN CLKFX180 PSCLK LOCKED STATUS[7:0] clock signal control signal PSDONE
DS031_67_110403
Figure 46: Digital Clock Manager The DCM can be configured to delay the completion of the Virtex-II configuration process until after the DCM has achieved lock. This guarantees that the chip does not begin operating until after the system clocks generated by the DCM have stabilized. The DCM has the following general control signals: * * * RST input pin: resets the entire DCM. LOCKED output pin: asserted High when all enabled DCM circuits have locked. STATUS output pins (active High): shown in Table 25.
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Phase Shifting
The DCM provides additional control over clock skew through either coarse- or fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 47 illustrates the effects of fine-phase shifting. For more information on DCM features, see the Virtex-II User Guide (UG002). Table 26 lists fine-phase shifting control pins, when used in variable mode. Table 26: Fine-Phase Shifting Control Pins Control Pin PSINCDEC PSEN PSCLK PSDONE Direction in in in out Function Increment or decrement Enable phase shift Clock for phase shift Active when completed
CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE
CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS negative) (PS/256) x PERIODCLKIN (PS positive)
CLKIN CLKOUT_PHASE_SHIFT = VARIABLE
CLKFB
(PS/256) x PERIODCLKIN (PS negative)
(PS/256) x PERIODCLKIN (PS positive)
DS031_48_101201
Figure 47: Fine-Phase Shifting Effects Two separate components of the phase shift range must be understood: * *
PHASE_SHIFT attribute range FINE_SHIFT_RANGE DCM timing parameter range
The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified under DCM Timing Parameters. Absolute range (fixed mode) = FINE_SHIFT_RANGE Absolute range (variable mode) = FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: * If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. If PERIODCLKIN 0.5 * FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode.
*
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Operating Modes
The frequency ranges of DCM input and output clocks depend on the operating mode specified, either low-frequency mode or high-frequency mode, according to Table 27. (For actual values, see QPro Virtex-II Switching Table 27: DCM Frequency Ranges Low-Frequency Mode Output Clock
CLK0, CLK180 CLK90, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180
Characteristics.) The CLK2X, CLK2X180, CLK90, and CLK270 outputs are not available in high-frequency mode. High or low-frequency mode is selected by an attribute.
High-Frequency Mode CLKIN Input
CLKIN_FREQ_DLL_HF NA NA CLKIN_FREQ_DLL_HF CLKIN_FREQ_FX_HF
CLKIN Input
CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_FX_LF
CLK Output
CLKOUT_FREQ_1X_LF CLKOUT_FREQ_1X_LF CLKOUT_FREQ_2X_LF CLKOUT_FREQ_DV_LF CLKOUT_FREQ_FX_LF
CLK Output
CLKOUT_FREQ_1X_HF NA NA CLKOUT_FREQ_DV_HF CLKOUT_FREQ_FX_HF
Locations/Organization
Virtex-II DCMs are placed on the top and the bottom of each block RAM and multiplier column. The number of DCMs depends on the device size, as shown in Table 28. Table 28: DCM Organization Device XQ2V1000 XQ2V3000 XQ2V6000 Columns 4 6 6 DCMs 8 12 12
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Active Interconnect Technology
Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores implementation. Virtex-II Active Interconnect Technology is a fully buffered programmable routing matrix. All routing resources are segmented to offer the advantages of a hierarchical solution. Virtex-II logic features like CLBs, IOBs, block RAM, multipliers, and DCMs are all connected to an identical switch matrix for access to global routing resources, as shown in Figure 48. Each Virtex-II device can be represented as an array of switch matrices with logic blocks attached, as illustrated in Figure 49.
Switch Matrix
CLB
Switch Matrix
Switch Matrix Switch Matrix
IOB
Switch Matrix
18Kb BRAM
MULT 18 x 18
Switch Matrix
DCM
Switch Matrix
DS031_55_101000
Figure 48: Active Interconnect Technology
Switch Matrix
IOB
Switch Matrix
IOB
Switch Matrix
IOB
Switch Matrix
DCM
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
SelectRAM
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Multiplier
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
DS031_34_110300
Figure 49: Routing Resources
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incremental design flow that is based on modular implementations. Total design time is reduced due to fewer and shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing resources, which are located in horizontal and vertical routing channels between each switch matrix. As shown in Figure 50, Virtex-II devices have fully buffered programmable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. Fanout has minimal impact on the performance of each net.
24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines
16 Direct Connections (total in all four directions)
8 Fast Connects
DS031_60_110403
Figure 50: Hierarchical Routing Resources In Figure 50: * Long lines are bidirectional wires that distribute signals across the device. Vertical and horizontal long lines span the full height and width of the device. Hex lines route signals to every third or sixth block away in all four directions. Organized in a staggered pattern, hex lines can only be driven from one end. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). Double lines route signals to every first or second block away in all four directions. Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). * * Direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. Fast connect lines are the internal CLB local interconnections from LUT outputs to LUT inputs.
*
Dedicated Routing
In addition to the global and local routing resources, dedicated signals are available: * * There are eight global clock nets per quadrant (see Global Clock Multiplexer Buffers). Horizontal routing resources are provided for on-chip 3-state buses. Four partitionable bus lines are provided per CLB row, permitting multiple buses within a row. (See 3-State Buffers.) Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-chain MUXCY
DS122 (v1.1) January 7, 2004 Product Specification
*
*
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QPro Virtex-II 1.5V Military QML Platform FPGAs Most programmable logic designers iterate through these steps several times in the process of completing a design.
*
*
output signals vertically to the adjacent slice. (See CLB/Slice Configurations.) One dedicated SOP chain per slice row (two per CLB row) propagates ORCY output logic signals horizontally to the adjacent slice. (See Sum of Products.) One dedicated shift chain per CLB connects the output of LUTs in shift-register mode to the input of the next LUT in shift-register mode (vertically) inside the CLB. (See Shift Registers, page 22.)
Design Entry
All Xilinx ISE development systems support the mainstream EDA design entry capabilities, ranging from schematic design to advanced HDL design methodologies. Given the high densities of the Virtex-II family, designs are created most efficiently using HDLs. To further improve their time to market, many Xilinx customers employ incremental, modular, and Intellectual Property (IP) design techniques. When properly used, these techniques further accelerate the logic design process. To enable designers to leverage existing investments in EDA tools and to ensure high-performance design flows, Xilinx jointly develops tools with leading EDA vendors, including: * * * * * * * Aldec Cadence Exemplar Mentor Graphics Model Technology Synopsys Synplicity
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Synthesis Environment (ISE) development systems, which support advanced design capabilities, including ProActive Timing Closure, integrated logic analysis, and the fastest place and route runtimes in the industry. ISE solutions enable designers to get the performance they need, quickly and easily. As a result of the ongoing cooperative development efforts between Xilinx and EDA Alliance partners, designers can take advantage of the benefits provided by EDA technologies in the programmable logic design process. Xilinx development systems are available in a number of easy to use configurations, collectively known as the ISE Series.
ISE Alliance
The ISE Alliance solution is designed to plug and play within an existing design environment. Built using industry standard data formats and netlists, these stable, flexible products enable Alliance EDA partners to deliver their best design automation capabilities to Xilinx customers, along with the time to market benefits of ProActive Timing Closure.
Complete information on Alliance Series partners and their associated design flows is available at http://www.xilinx.com on the Xilinx Alliance Series web page. The ISE Foundation product offers schematic entry and HDL design capabilities as part of an integrated design solution, enabling one-stop shopping. These capabilities are powerful, easy to use, and they support the full portfolio of Xilinx programmable logic devices. HDL design capabilities include a color-coded HDL editor with integrated language templates, state diagram entry, and Core generation capabilities.
ISE Foundation
The ISE Foundation solution delivers the benefits of true HDL-based design in a seamlessly integrated design environment. An intuitive project navigator, as well as powerful HDL design and two HDL synthesis tools, ensure that high-quality results are achieved quickly and easily. The ISE Foundation product includes: * * * State Diagram entry using Xilinx StateCAD Automatic HDL Testbench generation using Xilinx HDLBencher HDL Simulation using ModelSim XE
Synthesis
The ISE Alliance product is engineered to support advanced design flows with the industry's best synthesis tools. Advanced design methodologies include: * * * * Physical Synthesis Incremental synthesis RTL floorplanning Direct physical mapping
Design Flow
Virtex-II design flow proceeds as follows: * * * * Design Entry Synthesis Implementation Verification
The ISE Foundation product seamlessly integrates synthesis capabilities purchased directly from Exemplar, Synopsys, and Synplicity. In addition, it includes the capabilities of Xilinx Synthesis Technology. A benefit of having two seamlessly integrated synthesis engines within an ISE design flow is the ability to apply alternative sets of optimization techniques on designs, helping to ensure that designers can meet even the toughest timing requirements.
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Design Implementation
The ISE Series development systems include Xilinx timing-driven implementation tools, frequently called "place and route" or "fitting" software. This robust suite of tools enables the creation of an intuitive, flexible, tightly integrated design flow that efficiently bridges "logical" and "physical" design domains. This simplifies the task of defining a design, including its behavior, timing requirements, and optional layout (or floorplanning), as well as simplifying the task of analyzing reports generated during the implementation process. The Virtex-II implementation process is comprised of Synthesis, translation, mapping, place and route, and configuration file generation. While the tools can be run individually, many designers choose to run the entire implementation process with the click of a button. To assist those who prefer to script their design flows, Xilinx provides Xflow, an automated single command line process.
which are robust capabilities enabled by Xilinx exclusive hierarchical floorplanning capabilities. Another powerful design capability only available in the Xilinx design flow is "Modular Design", part of the Xilinx suite of team design tools, which enables autonomous design, implementation, and verification of design modules.
Incremental Synthesis
Xilinx unique hierarchical floorplanning capabilities enable designers to create a programmable logic design by isolating design changes within one hierarchical "logic block", and perform synthesis, verification, and implementation processes on that specific logic block. By preserving the logic in unchanged portions of a design, Xilinx incremental design makes the high-density design process more efficient. Xilinx hierarchical floorplanning capabilities can be specified using the high-level floorplanner or a preferred RTL floorplanner (see the Xilinx website for a list of supported EDA partners). When used in conjunction with one of the EDA partners' floorplanners, higher performance results can be achieved, as many synthesis tools use this more predictable detailed physical implementation information to establish more aggressive and accurate timing estimates when performing their logic optimizations.
Design Verification
In addition to conventional design verification using static timing analysis or simulation techniques, Xilinx offers powerful in-circuit debugging techniques using ChipScope ILA (Integrated Logic Analysis). The reconfigurable nature of Xilinx FPGAs means that designs can be verified in real time without the need for extensive sets of software simulation vectors. For simulation, the system extracts post-layout timing information from the design database, and back-annotates this information into the netlist for use by the simulator. The back annotation features a variety of patented Xilinx techniques, resulting in the industry's most powerful simulation flows. Alternatively, timing-critical portions of a design can be verified using the Xilinx static timing analyzer or a third party static timing analysis tool like Synopsys Prime Time, by exporting timing data in the STAMP data format. For in-circuit debugging, ChipScope ILA enables designers to analyze the real-time behavior of a device while operating at full system speeds. Logic analysis commands and captured data are transferred between the ChipScope software and ILA cores within the Virtex-II FPGA, using industry standard JTAG protocols. These JTAG transactions are driven over an optional download cable (MultiLINX or JTAG), connecting the Virtex device in the target system to a PC or workstation. ChipScope ILA was designed to look and feel like a logic analyzer, making it easy to begin debugging a design immediately. Modifications to the desired logic analysis can be downloaded directly into the system in a matter of minutes.
Modular Design
Xilinx innovative modular design capabilities take the incremental design process one step further by enabling the designer to delegate responsibility for completing the design, synthesis, verification, and implementation of a hierarchical "logic block" to an arbitrary number of designers assigning a specific region within the target FPGA for exclusive use by each of the team members. This team design capability enables an autonomous approach to design modules, changing the hand-off point to the lead designer or integrator from "my module works in simulation" to "my module works in the FPGA". This unique design methodology also leverages the Xilinx hierarchical floorplanning capabilities and enables the Xilinx (or EDA partner) floorplanner to manage the efficient implementation of very high-density FPGAs.
Configuration
Virtex-II devices are configured by loading application-specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general purpose inputs and outputs once configuration is complete. Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1, and M0 are dedicated pins. An additional pin, HSWAP_EN, is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configura-
Other Unique Features of Virtex-II Design Flow
Xilinx design flows feature a number of unique capabilities. Among these are efficient incremental HDL design flows,
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QPro Virtex-II 1.5V Military QML Platform FPGAs feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy chain is presented on the DOUT pin after the rising CCLK edge. The interface is identical to slave serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration.
tion. By default, HSWAP_EN is tied High (internal pull-up), which shuts off the pull-ups on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. Other dedicated pins are CCLK (the configuration clock pin), DONE, PROG_B, and the boundary-scan pins: TDI, TDO, TMS, and TCK. Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or an input accepting an externally generated clock. The configuration pins and boundary-scan pins are independent of the VCCO. The auxiliary power supply (VCCAUX) of 3.3V is used for these pins. All configuration pins are LVTTL 12 mA. (See QPro Virtex-II DC Characteristics.) A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected, then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the Virtex-II FPGA device with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, an active-Low Chip Select (CS_B) signal, and a Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If RDWR_B is asserted, configuration data is read out of the FPGA as part of a readback operation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback using the persist option. Multiple Virtex-II FPGAs can be configured using the SelectMAP mode, and can be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each device in turn and writing the appropriate data.
Configuration Modes
Virtex-II supports the following five configuration modes: * * * * * Slave-serial mode Master-serial mode Slave SelectMAP mode Master SelectMAP mode Boundary-Scan mode (IEEE 1532/IEEE 1149)
A detailed description of configuration modes is provided in the Virtex-II User Guide (UG002).
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of configuration data. The CCLK pin on the FPGA is an input in this mode. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of the externally generated CCLK. Multiple FPGAs can be daisy chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. Slave-serial mode is selected by applying <111> to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected.
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The device is configured byte-wide on a CCLK supplied by the Virtex-II FPGA. Timing is similar to the Slave SerialMAP mode except that CCLK is supplied by the Virtex-II FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In boundary-scan mode, dedicated pins are used for configuring the Virtex-II device. The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). Virtex-II device configuration using boundary scan is compliant with IEEE 1149.1-1993 standard and the new IEEE 1532 standard for In-System Configurable (ISC) devices. The IEEE 1532 standard is backward compliant with the IEEE 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-System Configurable (ISC) devices is intended to be programmed, reprogrammed, or tested on the board via a physical and logical protocol. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is the Virtex-II FPGA device that drives the configuration clock on the CCLK pin to a Xilinx Serial PROM, which in turn
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Table 29: Virtex-II Configuration Mode Pin Settings Configuration Mode (1) Master Serial Slave Serial Master SelectMAP Slave SelectMAP Boundary Scan M2 0 1 0 1 1 M1 0 1 1 1 0 M0 0 1 1 0 1 CCLK Direction Out In Out In N/A Data Width 1 1 8 8 1 Serial DOUT (2) Yes Yes No No No
Notes: 1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pullups are used. 2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices.
Table 30 lists the total number of bits required to configure each device. Table 30: Virtex-II Bitstream Lengths Device XQ2V1000 XQ2V3000 XQ2V6000 # of Configuration Bits 3,753,432 9,595,304 19,760,560
start-up sequence. The GSR signal resets all flip-flops on the device. The default start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Write Enable (GWE) signal is released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed via configuration options in software. In addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any or all DCMs, as well as the DCI.
Notes: 1. These values are only valid for STEPPING LEVEL 1. 2. Only STEPPING LEVEL 1 should be used with QPro devices.
Configuration Sequence
The configuration of Virtex-II devices is a three-phase process after Power On Reset or POR. POR occurs when VCCINT is greater than 1.2V, VCCAUX is greater than 2.5V, and VCCO (bank 4) is greater than 1.5V. Once the POR voltages have been reached, the three-phase process begins. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user. The INIT_B pin can be held Low using an open-drain driver. An open-drain is required since INIT_B is a bidirectional open-drain pin that is held Low by a Virtex-II FPGA device while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is signaled by the INIT_B pin going High, and the completion of the entire process is signaled by the DONE pin going High. The Global Set/Reset (GSR) signal is pulsed after the last frame of configuration data is written but before the
Readback
In this mode, configuration data from the Virtex-II FPGA device can be read back. Readback is supported only in the SelectMAP (master and slave) and Boundary Scan modes. Along with the configuration data, it is possible to read back the contents of all registers, distributed SelectRAM, and block RAM resources. This capability is used for real-time debugging. For more detailed configuration information, see the Virtex-II User Guide (UG002).
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two sets of three keys for triple-key Data Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the configuration data (bitstream) with a triple-key DES determined by the designer. The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin, when the device is not powered. Virtex-II devices can be configured with the corresponding encrypted bitstream, using any of the configuration modes described previously.
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QPro Virtex-II 1.5V Military QML Platform FPGAs while the rest of the chip remains in operation. Data is loaded on a column basis, with the smallest load unit being a configuration "frame" of the bitstream (device size dependent). Partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip.
A detailed description of how to use bitstream encryption is provided in the Virtex-II User Guide. Your local FAE can also provide specific information on this feature.
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be accomplished in either Slave SelectMAP mode or Boundary-Scan mode. Instead of resetting the chip and doing a full configuration, new data is loaded into a specified area of the chip,
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QPro Virtex-II Electrical Characteristics
QPro Virtex-II devices are only available with the -4 speed grade. QPro Virtex-II DC and AC characteristics are specified for military grade. Except for the operating temperature range, or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -4 speed grade military device are the same as for a -4 speed grade commercial device). All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information. All specifications are subject to change without notice.
QPro Virtex-II DC Characteristics
Table 31: Absolute Maximum Ratings Symbol VCCINT VCCAUX VCCO VBATT VREF VIN
(3)
Description(1) Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage Input voltage relative to GND (user and dedicated I/Os) Voltage applied to 3-state output (user and dedicated I/Os) Storage temperature (ambient) Maximum soldering temperature Operating junction temperature
(2)
Units
-0.5 to 1.65 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to VCCO + 0.5 -0.5 to VCCO + 0.5 -0.5 to 4.0 -65 to +150
V V V V V V V C C C
VTS TSTG TSOL TJ
+220 +125
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. 3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the device is not PCI compliant.
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Table 32: Recommended Operating Conditions Symbol VCCINT VCCAUX VCCO VBATT Description Internal supply voltage relative to GND, TC = -55 C to +125 C Internal supply voltage relative to GND, TJ = -55 C to +125 C Auxiliary supply voltage relative to GND, TC = -55 C to +125 C Auxiliary supply voltage relative to GND, TJ = -55 C to +125 C Supply voltage relative to GND, TC = -55 C to +125 C Supply voltage relative to GND, TJ = -55 C to +125 C Battery voltage relative to GND, TC = -55 C to +125 C Battery voltage relative to GND, TJ = -55 C to +125 C Package Ceramic Plastic Ceramic Plastic Ceramic Plastic Ceramic Plastic Min 1.425 1.425 3.135 3.135 1.2 1.2 1.0 1.0 Max 1.575 1.575 3.465 3.465 3.6 3.6 3.6 3.6 Units V V V V V V V V
Notes: 1. If battery is not used, do not connect VBATT. 2. Recommended maximum voltage droop for VCCAUX is 10 mV/ms. 3. The thresholds for Power On Reset are VCCINT > 1.2V, VCCAUX > 2.5V, and VCCO (Bank 4) > 1.5 V. 4. Limit the noise at the power supply to be within 200 mV peak-to-peak. 5. For power bypassing guidelines, see Xilinx Application Note XAPP623.
Table 33: DC Characteristics Over Recommended Operating Conditions Symbol VDRINT VDRI IREF IL CIN IRPU IRPD IBATT Description Data retention VCCINT voltage Data retention VCCAUX voltage VREF current per bank Input leakage current Input capacitance Pad pull-up (when selected) @ VIN = 0 V, VCCO = 3.3 V (sample tested) Pad pull-down (when selected) @ VIN = 3.6 V (sample tested) Battery supply current Device All All All All All All All All Note 1 Note 1 Min 1.2 2.5
-10 -10
Max
Units V V A A pF A A nA
+10 +10 10 250 250 100
Notes: 1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits.
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Table 34: Quiescent Supply Current Symbol Description Quiescent VCCINT supply current ICCINTQ Quiescent VCCO supply current(1,2) ICCOQ Quiescent VCCAUX supply current(1,2) ICCAUXQ Device
XQ2V1000 XQ2V3000 XQ2V6000 XQ2V1000 XQ2V3000 XQ2V6000 XQ2V1000 XQ2V3000 XQ2V6000 -
Min
Typical
100 200 250 1.0 2.0 2.0 10 20 25
Max
0.50 1.30 1.50 6.25 6.25 6.25 30 95 95
Units
A
mA
mA
Notes: 1. With no output current loads and no active input pull-up resistors. All I/O pins are 3-stated and floating. 2. If DCI or differential signaling is used, more accurate values can be obtained by using the Power Estimator or XPOWER. 3. Data are retained even if VCCO drops to 0 V. 4. Values specified for quiescent supply current parameters are Military Grade.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to ensure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. The VCCINT, VCCAUX, and VCCO power supplies shall each ramp on no faster than 200 s and no slower than 50 ms. Ramp on is defined as: 0 VDC to minimum supply voltages. Table 35 shows the minimum current required by QPro Virtex-II devices for proper power on and configuration. Power supplies can be turned on in any sequence. If any VCCO bank powers up before VCCAUX, then each bank draws up to 300 mA, worst case, until the VCCAUX powers on1. This does not harm the device. If the current is limited to the minimum value above, or larger, the device powers on properly after all three supplies have passed through their power on reset threshold voltages.
Once initialized and configured, use the power calculator to estimate current drain on these supplies. Table 35: Maximum Power On Current Required for QPro Virtex-II Devices
Device (mA) Current ICCINTMAX ICCAUXMAX ICCOMAX XQ2V1000 500 30 6.25 XQ2V3000 1300 95 6.25 XQ2V6000 1500 95 6.25
Notes: 1. Values specified for power on current parameters are Military Grade. 2. ICCOMAX values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential. Consult Xilinx Application Note XAPP623 for detailed information on power distribution system design. VCCAUX powers critical resources in the FPGA. Thus, VCCAUX is especially susceptible to power supply noise. Changes in VCCAUX voltage outside of 200 mV peak to peak should take place at a rate no faster than 10 mV per millisecond. Techniques to help reduce jitter and period distortion are provided in Xilinx Answer Record 13756, available at www.support.xilinx.com. VCCAUX can share a power plane with 3.3V VCCO, but only if VCCO does not have excessive noise. Using simultaneously switching output (SSO) limits are essential for keeping power supply noise to a minimum. Refer to XAPP689, "Managing Ground Bounce in Large FPGAs," to determine the number of simultaneously switching outputs allowed per bank at the package level.
1. The 300 mA is transient current (peak). It eventually disappears even if VCCAUX does not power up.
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DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are choTable 36: DC Input and Output Levels Input/Output Standard
LVTTL(1) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCI-X GTLP GTL HSTL I HSTL II HSTL III HSTL IV SSTL3 I SSTL3 II SSTL2 I SSTL2 II AGP
sen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
VIL V, Min
- 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5
VIH V, Min
2.0 2.0 1.7 65% VCCO 65% VCCO 50% VCCO 50% VCCO Note 2 VREF + 0.1 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 VREF + 0.2 VREF + 0.15 VREF + 0.15 VREF + 0.2
VOL V, Max
3.6 3.6 2.7 1.95 1.7 VCCO + 0.5 VCCO + 0.5 Note 2 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5 VCCO + 0.5
VOH V, Min
2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 90% VCCO 90% VCCO Note 2 n/a n/a VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VREF + 0.6 VREF + 0.8 VREF + 0.65 VREF + 0.80 90% VCCO
IOL mA
24 24 24 16 16 Note 2 Note 2 Note 2 36 40 8 16 24 48 8 16 7.6 15.2 Note 2
IOH mA
- 24 - 24 - 24 - 16 - 16 Note 2 Note 2 Note 2 n/a n/a -8 - 16 -8 -8 -8 - 16 - 7.6 - 15.2 Note 2
V, Max
0.8 0.8 0.7 35% VCCO 35% VCCO 30% VCCO 30% VCCO Note 2 VREF - 0.1 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF - 0.2 VREF - 0.15 VREF - 0.15 VREF - 0.2
V, Max
0.4 0.4 0.4 0.4 0.4 10% VCCO 10% VCCO Note 2 0.6 0.4 0.4 0.4 0.4 0.4 VREF - 0.6 VREF - 0.8 VREF - 0.65 VREF - 0.80 10% VCCO
Notes: 1. VOL and VOH for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA. 2. Tested according to the relevant specifications. 3. LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis.
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LDT Differential Signal DC Specifications (LDT_25)
Table 37: LDT DC Specifications DC Parameter Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOS Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude Symbol VOD VOD VOCM VOCM VID VID VICM VICM RT = 100 across Q and Q signals Conditions RT = 100 across Q and Q signals Min 500
-15
Typ 600
Max 700 15
Units mV mV mV mV mV mV mV mV
560
-15
600
640 15
200
-15
600
1000 15
500
-15
600
700 15
LVDS DC Specifications (LVDS_33 and LVDS_25)
Table 38: LVDS DC Specifications
DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25 V Differential input voltage = 350 mV 0.925 250 1.125 100 0.2 350 1.2 350 1.25 400 1.375 N/A VCCO - 0.5 Conditions Min Typ 3.3 or 2.5 1.575 Max Units V V V mV V mV V
Extended LVDS DC Specifications (LVDSEXT_33 and LVDSEXT_25)
Table 39: Extended LVDS DC Specifications
DC Parameter Supply Voltage Output High voltage for Q and Q Output Low voltage for Q and Q Differential output voltage (Q - Q), Q = High (Q - Q), Q = High Output common-mode voltage Differential input voltage (Q - Q), Q = High (Q - Q), Q = High Input common-mode voltage Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25 V Differential input voltage = 350 mV 0.705 440 1.125 100 0.2 1.200 350 1.25 820 1.375 N/A VCCO - 0.5 Conditions Min Typ 3.3 or 2.5 1.785 Max Units V V V mV V mV V
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LVPECL DC Specifications
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower Table 40: LVPECL DC Specifications DC Parameter VCCO VOH VOL VIH VIL Differential Input Voltage 1.8 0.96 1.49 0.86 0.3 Min 3.0 2.11 1.27 2.72 2.125
-
common-mode ranges. Table 40 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-II User Guide.
Max
Min 3.3 1.92 1.06 1.49 0.86 0.3
Max
Min 3.6
Max
Units V
2.28 1.43 2.72 2.125
-
2.13 1.30 1.49 0.86 0.3
2.41 1.57 2.72 2.125
-
V V V V V
QPro Virtex-II Switching Characteristics
Switching characteristics in this document are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 41 correlates the current status of each QPro Virtex-II device with a corresponding speed grade designation. Table 41: QPro Virtex-II Device Speed Grade Designations Speed Grade Designations Device XQ2V1000 XQ2V3000 XQ2V6000 Advance Preliminary Production
-4 -4 -4
All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the Xilinx static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all QPro Virtex-II devices.
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IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with Table 42: IOB Input Switching Characteristics Description
Propagation Delays
the values shown in IOB Input Switching Characteristics Standard Adjustments, page 53.
Symbol
Device
Min
Max
Units
Pad to I output, no delay Pad to I output, with delay
TIOPI TIOPID
All XQ2V1000 XQ2V3000 XQ2V6000
-
0.88 2.43 2.49 2.66
ns ns ns ns
Propagation Delays
Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay
TIOPLI TIOPLID
All XQ2V1000 XQ2V3000 XQ2V6000
-
1.05 4.09 4.20 4.55 0.77
ns ns ns ns ns
Clock CLK to output IQ
TIOCKIQ
All
Setup and Hold Times with Respect to Clock at IOB Input Register
Pad, no delay Pad, with delay
TIOPICK/TIOICKP TIOPICKD/TIOICK
PD
All XQ2V1000 XQ2V3000 XQ2V6000
1.06/-0.45 4.10/-2.58 4.22/-2.66 4.56/-2.90 0.24/ 0.04 0.34
-
ns ns ns ns ns ns
ICE input SR input (IFF, synchronous)
Set/Reset Delays
TIOICECK/TIOCKI
CE
All All
TIOSRCKI
SR input to IQ (asynchronous) GSR to output IQ
TIOSRIQ TGSRQ
All All
1.40 6.88
ns ns
Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 46.
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IOB Input Switching Characteristics Standard Adjustments
Table 43: IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments TILVTTL TILVCMOS33 TILVCMOS25 TILVCMOS18 TILVCMOS15 TILVDS_25 TILVDS_33 TILVPECL_33 TIPCI33_3 TIPCI66_3 TIPCIX TIGTL TIGTLP TIHSTL_I TIHSTL_II TIHSTL_III TIHSTL_IV TIHSTL_I_18 TIHSTL_II_18 TIHSTL_III_18 TIHSTL_IV_18 TISSTL2_I TISSTL2_II TISSTL3_I TISSTL3_II TIAGP TILVDCI_33 TILVDCI_25 TILVDCI_18 TILVDCI_15 TILVDCI_DV2_33 TILVDCI_DV2_25 TILVDCI_DV2_18 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVDS_25 LVDS_33 LVPECL PCI, 33 MHz, 3.3 V PCI, 66 MHz, 3.3 V PCI-X, 133 MHz, 3.3 V GTL GTLP HSTL I HSTL II HSTL III HSTL IV HSTL I_18 HSTL II_18 HSTL III_18 HSTL IV_18 SSTL2 I SSTL2 II SSTL3 I SSTL3 II AGP LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_33 LVDCI_DV2_25 LVDCI_DV2_18
0.00 0.00 0.12 0.49 1.15 0.69 0.69 0.69 0.00 0.00 0.00 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.40 0.40 0.40 0.00 0.12 0.49 1.14 0.00 0.12 0.49
Symbol
Standard
Value
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 43: IOB Input Switching Characteristics Standard Adjustments (Continued) Description Standard-specific data input delay adjustments Symbol TILVDCI_DV2_15 TIGTL_DCI TIGTLP_DCI TIHSTL_I_DCI TIHSTL_II_DCI TIHSTL_III_DCI TIHSTL_IV_DCI TIHSTL_I_DCI_18 TIHSTL_II_DCI_18 TIHSTL_III_DCI_18 TIHSTL_IV_DCI_18 TISSTL2_I_DCI TISSTL2_II_DCI TISSTL3_I_DCI TISSTL3_II_DCI TILDT_25 TIULVDS_25
Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 46.
R
Standard LVDCI_DV2_15 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL2_I_DCI SSTL2_II_DCI SSTL3_I_DCI SSTL3_II_DCI LDT_25 ULVDS_25
Value
1.14 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.40 0.40 0.56 0.56
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 56. Table 44: IOB Output Switching Characteristics Description Propagation Delays O input to Pad O input to Pad via transparent latch 3-State Delays T input to Pad high-impedance(1) T input to valid data on Pad T input to Pad high-impedance via transparent latch(1) TIOTHZ TIOTON TIOTLPHZ TIOTLPON TGTS TIOCKP (synchronous)(1) TIOCKHZ TIOCKON TIOOCK/TIOCKO TIOOCECK/TIOCKOCE TIOSRCKO/TIOCKOSR TIOTCK/TIOCKT TIOTCECK/TIOCKTCE TIOSRCKT/TIOCKTSR TIOSRP TIOSRHZ TIOSRON TIOGSRQ
0.64 1.67 1.01 2.04 5.98
Symbol
Min
Max
Units
TIOOP TIOOLP
1.74 2.11
ns ns
ns ns ns ns ns
T input to valid data on Pad via transparent latch GTS to Pad high-impedance(1) Sequential Delays Clock CLK to Pad Clock CLK to Pad high-impedance
2.15 1.20 2.22
ns ns ns
Clock CLK to valid data on Pad (synchronous) Setup and Hold Times Before/After Clock CLK O input OCE input SR input (OFF) 3-State Setup Times, T input 3-State Setup Times, TCE input 3-State Setup Times, SR input (TFF) Set/Reset Delays SR input to Pad (asynchronous) SR input to Pad high-impedance (asynchronous)(1) SR input to valid data on Pad (asynchronous) GSR to Pad
Notes: 1. The 3-state turn-off delays should not be adjusted.
0.39/-0.11 0.24/-0.08 0.34/-0.07 0.35/-0.08 0.24/-0.08 0.34/-0.07
ns ns ns ns ns ns
2.98 1.92 2.95 6.88
ns ns ns ns
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IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 45: IOB Output Switching Characteristics Standard Adjustments
Description Output Delay Adjustments Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 TOLVTTL_S8 TOLVTTL_S12 TOLVTTL_S16 TOLVTTL_S24 TOLVTTL_F2 TOLVTTL_F4 TOLVTTL_F6 TOLVTTL_F8 TOLVTTL_F12 TOLVTTL_F16 TOLVTTL_F24 TOLVDS_25 TOLVDS_33 TOLVDSEXT_25 TOLVDSEXT_33 TOLDT_25 TOBLVDS_25 TOULVDS_25 TOLVPECL_33 TOPCI33_3 TOPCI66_3 TOPCIX TOGTL TOGTLP TOHSTL_I TOHSTL_II TOHSTL_III TOHSTL_IV TOHSTL_I_18 TOHSTL_II_18 TOHSTL_III_18 LVTTL, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVTTL, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVDS LVDS LVDS LVDS LDT BLVDS ULVDS LVPECL PCI, 33 MHz, 3.3 V PCI, 66 MHz, 3.3 V PCI-X, 133 MHz, 3.3 V GTL GTLP HSTL I HSTL II HSTL III HSTL IV HSTL I_18 HSTL II_18 HSTL III_18 10.68 6.55 4.66 3.26 2.63 1.93 1.43 7.39 3.17 1.78 0.52 0.00 -0.15 -0.26 -0.36 -0.29 -0.21 -0.19 -0.23 0.76 -0.23 0.33 1.31 -0.01 -0.01 -0.36 -0.20 0.29 -0.17 -0.19 -0.45 -0.04 -0.20 -0.18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Standard Value Units
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Table 45: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) Symbol TOHSTL_IV_18 TOSSTL2_I TOSSTL2_II TOSSTL3_I TOSSTL3_II TOAGP TOLVCMOS33_S2 TOLVCMOS33_S4 TOLVCMOS33_S6 TOLVCMOS33_S8 TOLVCMOS33_S12 TOLVCMOS33_S16 TOLVCMOS33_S24 TOLVCMOS33_F2 TOLVCMOS33_F4 TOLVCMOS33_F6 TOLVCMOS33_F8 TOLVCMOS33_F12 TOLVCMOS33_F16 TOLVCMOS33_F24 TOLVCMOS25_S2 TOLVCMOS25_S4 TOLVCMOS25_S6 TOLVCMOS25_S8 TOLVCMOS25_S12 TOLVCMOS25_S16 TOLVCMOS25_S24 TOLVCMOS25_F2 TOLVCMOS25_F4 TOLVCMOS25_F6 TOLVCMOS25_F8 TOLVCMOS25_F12 TOLVCMOS25_F16 TOLVCMOS25_F24 TOLVCMOS18_S2 TOLVCMOS18_S4 TOLVCMOS18_S6 TOLVCMOS18_S8 Standard HSTL IV_18 SSTL2 I SSTL2 II SSTL3 I SSTL3 II AGP LVCMOS33, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS33, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS25, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS25, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS18, Slow, 2 mA 4 mA 6 mA 8 mA Value -0.44 0.24 -0.18 0.33 -0.05 -0.31 8.70 4.95 3.78 2.60 2.16 1.40 1.34 6.60 2.81 1.45 0.54 0.31 -0.15 -0.23 10.33 5.67 5.13 4.38 3.22 2.67 2.27 4.60 1.30 0.81 0.37 0.03 -0.21 -0.40 17.71 11.57 8.53 7.78 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) Symbol TOLVCMOS18_S12 TOLVCMOS18_S16 TOLVCMOS18_F2 TOLVCMOS18_F4 TOLVCMOS18_F6 TOLVCMOS18_F8 TOLVCMOS18_F12 TOLVCMOS18_F16 TOLVCMOS15_S2 TOLVCMOS15_S4 TOLVCMOS15_S6 TOLVCMOS15_S8 TOLVCMOS15_S12 TOLVCMOS15_S16 TOLVCMOS15_F2 TOLVCMOS15_F4 TOLVCMOS15_F6 TOLVCMOS15_F8 TOLVCMOS15_F12 TOLVCMOS15_F16 TOLVDCI_33 TOLVDCI_25 TOLVDCI_18 TOLVDCI_15 TOLVDCI_DV2_33 TOLVDCI_DV2_25 TOLVDCI_DV2_18 TOLVDCI_DV2_15 TOGTL_DCI TOGTLP_DCI TOHSTL_I_DCI TOHSTL_II_DCI TOHSTL_III_DCI TOHSTL_IV_DCI TOHSTL_I_DCI_18 TOHSTL_II_DCI_18 TOHSTL_III_DCI_18 TOHSTL_IV_DCI_18 Standard 12 mA 16 mA LVCMOS18, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVCMOS15, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVCMOS15, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_33 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 Value 6.28 6.02 6.30 2.15 0.94 0.80 0.30 0.26 21.50 14.48 13.66 11.06 10.25 9.31 5.78 2.27 1.66 1.05 0.84 0.75 0.84 0.88 0.95 2.06 0.13 0.03 0.48 1.36 -0.35 -0.17 0.26 0.07 -0.20 -0.52 0.06 -0.03 -0.16 -0.47 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 45: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) Symbol TOSSTL2_I_DCI TOSSTL2_II_DCI TOSSTL3_I_DCI TOSSTL3_II_DCI Standard SSTL2_I_DCI SSTL2_II_DCI SSTL3_I_DCI SSTL3_II_DCI Value 0.14 -0.11 0.17 0.09 Units ns ns ns ns
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I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 46 shows the test setup parameters used for measuring Input standard adjustments (see Table 43, page 53). Table 46: Input Delay Measurement Methodology
Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCI-X GTL GTLP HSTL Class I HSTL Class II HSTL Class III HSTL Class IV SSTL3 Class I & II SSTL2 Class I & II AGP-2X LVDS25 LVDS33 LVDSEXT25 LVDSEXT33 ULVDS25 LDT25 LVPECL VL (1) 0 0 0 0 0 VH (1) 3.0 3.3 2.5 1.8 1.5 Per PCI Specification Per PCI Specification Per PCI-X Specification VREF - 0.2 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 1.00 VREF - 0.75 VREF - (0.2 xVCCO) 1.2 - 0.125 1.2 - 0.125 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125 0.6 - 0.125 1.6 - 0.3 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + (0.2 x VCCO) 1.2 + 0.125 1.2 + 0.125 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 0.6 + 0.125 1.6 + 0.3 VREF VREF VREF VREF VREF VREF VREF VREF
VMEAS
(3,4)
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pf) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. (See Virtex-II Platform FPGA User Guide for details.) The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown in Figure 51. Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. (IBIS models can be found on the web at http://support.xilinx.com/support/sw_ibis.htm.) Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 47. 2. Record the time to VMEAS . 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Output Standard Adjustment value (Table 45) to yield the actual worst-case propagation delay (clock-to-input) of the PCB trace.
VREF
(2,4)
1.4 1.65 1.25 0.9 0.75
- - - - - - - - 0.80 1.0 0.75 0.75 0.90 0.90 1.5 1.25 Per AGP Spec
VREF FPGA Output
VREF 1.2 1.2 1.2 1.2 0.6 0.6 1.6
RREF
VMEAS (voltage level at which delay measurement is taken) CREF
(probe capacitance)
ds083-3_06a_092503
Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. See Virtex-II Platform FPGA User Guide for min/max specifications. 3. Input voltage level from which measurement starts. 4. Note that this is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 51.
Figure 51: Generalized Test Setup
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 47: Output Delay Measurement Methodology
Standard LVDS25 LVDSEXT25 LVDS33 LVDSEXT33 BLVDS LDT_25 LVPECL25 LVDCI33 LVDCI25 LVDCI18 3.3 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.5 1.5 1.25 1.25 0.9 0.9 0 3.3 LVDCI15 HSTL DCI Class I HSTL DCI C0lass II HSTL DCI Class III HSTL DCI Class IV HSTL18 DCI Class I HSTL18 DCI Class II HSTL18 DCI Class III HSTL18 DCI Class IV SSTL3 DCI Class I SSTL3 DCI Class II SSTL2 DCI Class I SSTL2 DCI Class II SSTL18 DCI Class I SSTL18 DCI Class II GTL DCI GTLP DCI RREF (ohms) 50 50 50 50 1M 50 1M 1M 1M 1M 1M 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 CREF(1) (pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMEAS (V) VREF VREF VREF VREF 1.2 VREF 1.23 1.65 1.25 0.9 0.75 VREF VREF 0.9 0.9 VREF VREF 1.1 1.1 VREF VREF VREF VREF VREF VREF 0.8 1.0 VREF (V) 1.2 1.2 1.2 1.2 0 0.6 0 0 0 0 0 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.5 1.5 1.25 1.25 0.9 0.9 1.2 1.5
Table 47: Output Delay Measurement Methodology
Standard LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 - rising edge PCI33_3 - falling edge PCI66_3 - rising edge PCI66_3 - falling edge PCI-X - rising edge PCI-X - falling edge GTL GTLP HSTL Class I HSTL Class II HSTL Class III HSTL Class IV HSTL18 Class I HSTL18 Class II HSTL18 Class III HSTL18 Class IV SSTL3 Class I SSTL3 Class II SSTL2 Class I SSTL2 Class II SSTL18 Class I SSTL18 Class II AGP-2X - rising edge AGP-2X - falling edge RREF (ohms) 1M 1M 1M 1M 1M 25 25 25 25 25 25 25 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 50 CREF(1) (pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMEAS (V) 1.4 1.65 1.25 0.9 0.75 0.94 2.03 0.94 2.03 0.94 2.03 0.8 1.0 VREF VREF 0.9 0.9 VREF VREF 1.1 1.1 VREF VREF VREF VREF VREF VREF 0.94 2.03 VREF (V) 0 0 0 0 0 0 3.3 0 3.3
Notes: 1. CREF is the capacitance of the probe, nominally 0 pF.
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Clock Distribution Switching Characteristics
Table 48: Clock Distribution Switching Characteristics Description Global Clock Buffer I input to O output Symbol TGIO
Value 0.59
Units ns
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 49). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 49: CLB Switching Characteristics Description
Combinatorial Delays
Symbol
Min
Max
Units
4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output FXINA or FXINB inputs to Y output via MUXFX FXINA input to FX output via MUXFX FXINB input to FX output via MUXFX SOPIN input to SOPOUT output via ORCY Incremental delay routing through transparent latch to XQ/YQ outputs
Sequential Delays
TILO TIF5 TIF5X TIFXY TINAFX TINBFX TSOPSOP TIFNCTL
-
0.44 0.72 0.95 0.45 0.32 0.32 0.44 0.51
ns ns ns ns ns ns ns ns
FF Clock CLK to XQ/YQ outputs Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
TCKO TCKLO TDICK/TCKDI TDYCK/TCKDY TDXQK/TCKDX TCECK/TCKCE TSRCK/TSCKR TCH TCL TRPW TRQ FTOG
-
0.57 0.68
ns ns
BX/BY inputs DY inputs DX inputs CE input SR/BY inputs (synchronous)
Clock CLK
0.37/-0.09 0.37/-0.09 0.37/-0.09 0.24/-0.08 0.26/-0.03
-
ns ns ns ns ns
Minimum Pulse Width, High Minimum Pulse Width, Low
Set/Reset
0.77 0.77
-
ns ns
Minimum Pulse Width, SR/BY inputs Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Toggle Frequency (MHz) (for export control)
0.77 -
1.34 650
ns ns MHz
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CLB Distributed RAM Switching Characteristics
Table 50: CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active) in 16 x 1 mode Clock CLK to X/Y outputs (WE active) in 32 x 1 mode Clock CLK to F5 output Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) F/G address inputs SR input (WS) Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time TWPH TWPL TWC
0.72 0.72 1.44 -
Symbol
Min
Max
Units
TSHCKO16 TSHCKO32 TSHCKOF5 TDS/TDH TAS/TAH TWES/TWEH
-
2.05 2.49 2.23
ns ns ns
0.67/-0.11 0.50/ 0.00 0.53/-0.01
-
ns ns ns
ns ns ns
CLB Shift Register Switching Characteristics
Table 51: CLB Shift Register Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs Clock CLK to X/Y outputs Clock CLK to XB output via MC15 LUT output Clock CLK to YB output via MC15 LUT output Clock CLK to Shiftout Clock CLK to F5 output Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) SR input (WS) Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low TSRPH TSRPL
0.72 0.72 -
Symbol
Min
Max
Units
TREG TREG32 TREGXB TREGYB TCKSH TREGF5 TSRLDS/TSRLDH TWSS/TWSH
-
2.92 3.35 2.82 2.75 2.43 3.09
ns ns ns ns ns ns
0.67/-0.09 0.24/-0.08
-
ns ns
ns ns
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Multiplier Switching Characteristics
Table 52 and Table 53 provide timing information for QPro Virtex-II multiplier blocks, available in stepping revisions of QPro Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales representative. Table 52: Enhanced Multiplier Switching Characteristics
Description Propagation Delay to Output Pin Input to Pin 35 Input to Pin 34 Input to Pin 33 Input to Pin 32 Input to Pin 31 Input to Pin 30 Input to Pin 29 Input to Pin 28 Input to Pin 27 Input to Pin 26 Input to Pin 25 Input to Pin 24 Input to Pin 23 Input to Pin 22 Input to Pin 21 Input to Pin 20 Input to Pin 19 Input to Pin 18 Input to Pin 17 Input to Pin 16 Input to Pin 15 Input to Pin 14 Input to Pin 13 Input to Pin 12 Input to Pin 11 Input to Pin 10 Input to Pin 9 Input to Pin 8 Input to Pin 7 Input to Pin 6 Input to Pin 5 Input to Pin 4 Input to Pin 3 Input to Pin 2 Input to Pin 1 Input to Pin 0 TMULT_P35 TMULT_P34 TMULT_P33 TMULT_P32 TMULT_P31 TMULT_P30 TMULT_P29 TMULT_P28 TMULT_P27 TMULT_P26 TMULT_P25 TMULT_P24 TMULT_P23 TMULT_P22 TMULT_P21 TMULT_P20 TMULT_P19 TMULT_P18 TMULT_P17 TMULT_P16 TMULT_P15 TMULT_P14 TMULT_P13 TMULT_P12 TMULT_P11 TMULT_P10 TMULT_P9 TMULT_P8 TMULT_P7 TMULT_P6 TMULT_P5 TMULT_P4 TMULT_P3 TMULT_P2 TMULT_P1 TMULT_P0 5.91 5.79 5.66 5.54 5.42 5.29 5.17 5.05 4.92 4.80 4.68 4.56 4.43 4.31 4.19 4.06 3.94 3.82 3.69 3.57 3.45 3.33 3.20 3.08 2.96 2.83 2.71 2.59 2.46 2.34 2.22 2.10 1.97 1.85 1.73 1.60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min Max Units
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Table 53: Pipelined Multiplier Switching Characteristics
Description Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin 35 Clock to Pin 34 Clock to Pin 33 Clock to Pin 32 Clock to Pin 31 Clock to Pin 30 Clock to Pin 29 Clock to Pin 28 Clock to Pin 27 Clock to Pin 26 Clock to Pin 25 Clock to Pin 24 Clock to Pin 23 Clock to Pin 22 Clock to Pin 21 Clock to Pin 20 Clock to Pin 19 Clock to Pin 18 Clock to Pin 17 Clock to Pin 16 Clock to Pin 15 Clock to Pin 14 Clock to Pin 13 Clock to Pin 12 Clock to Pin 11 Clock to Pin 10 Clock to Pin 9 Clock to Pin 8 Clock to Pin 7 Clock to Pin 6 Clock to Pin 5 Clock to Pin 4 Clock to Pin 3 Clock to Pin 2 Clock to Pin 1 Clock to Pin 0 TMULTCK_P35 TMULTCK_P34 TMULTCK_P33 TMULTCK_P32 TMULTCK_P31 TMULTCK_P30 TMULTCK_P29 TMULTCK_P28 TMULTCK_P27 TMULTCK_P26 TMULTCK_P25 TMULTCK_P24 TMULTCK_P23 TMULTCK_P22 TMULTCK_P21 TMULTCK_P20 TMULTCK_P19 TMULTCK_P18 TMULTCK_P17 TMULTCK_P16 TMULTCK_P15 TMULTCK_P14 TMULTCK_P13 TMULTCK_P12 TMULTCK_P11 TMULTCK_P10 TMULTCK_P9 TMULTCK_P8 TMULTCK_P7 TMULTCK_P6 TMULTCK_P5 TMULTCK_P4 TMULTCK_P3 TMULTCK_P2 TMULTCK_P1 TMULTCK_P0 3.74 3.61 3.49 3.37 3.25 3.12 3.00 2.88 2.75 2.63 2.51 2.38 2.26 2.14 2.02 1.89 1.77 1.65 1.52 1.40 1.28 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TMULIDCK/TMULCKID TMULIDCK_CE/TMULCKID_CE TMULIDCK_RST/TMULCKID_RST 3.89/0.00 0.86/0.00 0.86/0.00 ns ns ns Symbol Min Max Units
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Block SelectRAM Switching Characteristics
Table 54: Block SelectRAM Switching Characteristics Description
Sequential Delays
Symbol
Min
Min
Units
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
TBCKO TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE TBRCK/TBCKR TBWCK/TBCKW TBPWH TBPWL
-
2.65
ns
ADDR inputs DIN inputs EN input RST input WEN input
Clock CLK
0.36/ 0.00 0.36/ 0.00 1.20/-0.58 1.65/-0.90 0.72/-0.25
-
ns ns ns ns ns
Minimum Pulse Width, High Minimum Pulse Width, Low
1.48 1.48
-
ns ns
TBUF Switching Characteristics
Table 55: TBUF Switching Characteristics Description Combinatorial Delays IN input to OUT output TRI input to OUT output high-impedance TRI input to valid data on OUT output TIO TOFF TON
0.58 0.55 0.55
Symbol
Min
Max
Units
ns ns ns
JTAG Test Access Port Switching Characteristics
Table 56: JTAG Test Access Port Switching Characteristics Description TMS and TDI Setup times before TCK TMS and TDI Hold times after TCK Output delay from clock TCK to output TDO Maximum TCK clock frequency Symbol TTAPTK TTCKTAP TTCKTDO FTCK Min 5.5 0.0 Max 10.0 33 Units ns ns ns MHz
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QPro Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM
Table 57: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM Description LVTTL Global Clock Input to Output delay using Output flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 56. Global Clock and OFF with DCM
TICKOFDCM XQ2V1000 XQ2V3000 XQ2V6000 2.76 2.88 3.45 ns ns ns
Symbol
Device
Value
Units
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured with a 35 pF external capacitive load. The only time it is not 50% of VCC threshold is with LVCMOS. For other I/O standards and different loads, see Table 47. 3. DCM output jitter is included in the measurement.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM
Table 58: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM Description LVTTL Global Clock Input to Output Delay using Output flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 56. Global Clock and OFF without DCM
TICKOF XQ2V1000 XQ2V3000 XQ2V6000 5.90 6.62 7.22 ns ns ns
Symbol
Device
Value
Units
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 47.
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QPro Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, with DCM
Table 59: Global Clock Setup and Hold for LVTTL Standard, with DCM Description Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 53.
No Delay Global Clock and IFF with DCM TPSDCM/TPHDCM XQ2V1000 XQ2V3000 XQ2V6000 1.84/-0.76 1.96/-0.76 1.96/-0.76 ns ns ns
Symbol
Device
Value
Units
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load.
Global Clock Setup and Hold for LVTTL Standard, without DCM
Table 60: Global Clock Setup and Hold for LVTTL Standard, without DCM Description Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard.(1) For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 53. Full Delay Global Clock and IFF(2) without DCM
TPSFD/TPHFD XQ2V1000 XQ2V3000 XQ2V6000 2.21/ 0.00 2.21/ 0.00 2.21/ 0.50 ns ns ns
Symbol
Device
Value
Units
Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. IFF = Input Flip-Flop or Latch 3. These values are parametrically measured.
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QPro Virtex-II 1.5V Military QML Platform FPGAs
DCM Timing Parameters
All devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. All output jitter and phase specifications are determined through statistical measurement at the package pins.
Operating Frequency Ranges
Table 61: Operating Frequency Ranges
Description Output Clocks (Low Frequency Mode) CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_LF_Min CLKOUT_FREQ_1X_LF_Max CLK2X, CLK2X180 CLKOUT_FREQ_2X_LF_Min CLKOUT_FREQ_2X_LF_Max CLKDV CLKOUT_FREQ_DV_LF_Min CLKOUT_FREQ_DV_LF_Max CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_Min CLKOUT_FREQ_FX_LF_Max Input Clocks (Low Frequency Mode) CLKIN (using DLL outputs) (1), (3) CLKIN_FREQ_DLL_LF_Min CLKIN_FREQ_DLL_LF_Max CLKIN (using CLKFX outputs) (2), (3) CLKIN_FREQ_FX_LF_Min CLKIN_FREQ_FX_LF_Max PSCLK PSCLK_FREQ_LF_Min PSCLK_FREQ_LF_Max Output Clocks (High Frequency Mode) CLK0, CLK180 CLKOUT_FREQ_1X_HF_Min CLKOUT_FREQ_1X_HF_Max CLKDV CLKOUT_FREQ_DV_HF_Min CLKOUT_FREQ_DV_HF_Max CLKFX, CLKFX180 CLKOUT_FREQ_FX_HF_Min CLKOUT_FREQ_FX_HF_Max Input Clocks (High Frequency Mode) CLKIN (using DLL outputs) (1), (3) CLKIN_FREQ_DLL_HF_Min CLKIN_FREQ_DLL_HF_Max CLKIN (using CLKFX outputs) (2), (3) CLKIN_FRQ_FX_HF_Min CLKIN_FRQ_FX_HF_Max PSCLK PSCLK_FREQ_HF_Min PSCLK_FREQ_HF_Max 48.00 360.00 50.00 270.00 0.01 360.00 MHz MHz MHz MHz MHz MHz 48.00 360.00 3.00 240.00 210.00 270.00 MHz MHz MHz MHz MHz MHz 24.00 180.00 1.00 210.00 0.01 360.00 MHz MHz MHz MHz MHz MHz 24.00 180.00 48.00 360.00 1.50 120.00 24.00 210.00 MHz MHz MHz MHz MHz MHz MHz MHz Symbol Constraints Value Units
Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
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Input Clock Tolerances
Table 62: Input Clock Tolerances
Constraints Description Symbol FCLKIN Min Max Units
Input Clock Low/High Pulse Width PSCLK PSCLK_PULSE < 1MHz 1 - 10 MHz 10 - 25 MHz 25 - 50 MHz 50 - 100 MHz 100 - 150 MHz PSCLK and CLKIN(2) PSCLK_PULSE and CLKIN_PULSE 150 - 200 MHz 200 - 250 MHz 250 - 300 MHz 300 - 350 MHz 350 - 400 MHz > 400 MHz Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF 300 300 ps ps 25.00 25.00 10.00 5.00 3.00 2.40 2.00 1.80 1.50 1.30 1.15 1.05 ns ns ns ns ns ns ns ns ns ns ns ns
Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) Input Clock Period Jitter (Low Frequency Mode) CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_FX_LF 1 1 ns ns CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF 150 150 ps ps
Input Clock Period Jitter (High Frequency Mode) CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) Feedback Clock Path Delay Variation CLKFB off-chip feedback CLKFB_DELAY_VAR_EXT 1 ns CLKIN_PER_JITT_DLL_HF CLKIN_PER_JITT_FX_HF 1 1 ns ns
Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. If the DCM phase shift feature is used and the CLKIN frequency > 200 MHz, the CLKIN duty cycle must be within 5% (45/55 to 55/45).
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Output Clock Jitter
Table 63: Output Clock Jitter
Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 CLKOUT_PER_JITT_FX 100 150 150 150 200 150 300 Note 1 ps ps ps ps ps ps ps ps Symbol Constraints Value Units
Notes: 1. Values for this parameter are available at http://www.xilinx.com.
Output Clock Phase Alignment
Table 64: Output Clock Phase Alignment
Description Phase Offset Between CLKIN and CLKFB CLKIN/CLKFB Phase Offset Between Any DCM Outputs All CLK* outputs Duty Cycle Precision DLL outputs(1) CLKFX outputs CLKOUT_DUTY_CYCLE_DLL(2) CLKOUT_DUTY_CYCLE_FX 150 100 ps ps CLKOUT_PHASE 140 ps CLKIN_CLKFB_PHASE 50 ps Symbol Constraints Value Units
Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. 3. Specification also applies to PSCLK.
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Miscellaneous Timing Parameters
Table 65: Miscellaneous Timing Parameters
Description Time Required to Achieve LOCK Using DLL outputs(1) LOCK_DLL LOCK_DLL_60 LOCK_DLL_50_60 LOCK_DLL_40_50 LOCK_DLL_30_40 LOCK_DLL_24_30 Using CLKFX outputs LOCK_FX_MIN LOCK_FX_MAX Additional lock time with fine-phase shifting Fine-Phase Shifting Absolute shifting range Delay Lines Tap delay resolution DCM_TAP_MIN DCM_TAP_MAX 30.0 60.0 ps ps FINE_SHIFT_RANGE 10.0 ns LOCK_DLL_FINE_SHIFT > 60MHz 50 - 60 MHz 40 - 50 MHz 30 - 40 MHz 24 - 30 MHz 20.0 25.0 50.0 90.0 120.0 10.0 10.0 50.0 s s s s s ms ms s Symbol Constraints FCLKIN
Value
Units
Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. Specification also applies to PSCLK.
Frequency Synthesis
Table 66: Frequency Synthesis Attribute CLKFX_MULTIPLY CLKFX_DIVIDE Min 2 1 Max 32 32
Parameter Cross Reference
Table 67: Parameter Cross Reference Libraries Guide DLL_CLKOUT_{MIN|MAX}_LF DFS_CLKOUT_{MIN|MAX}_LF DLL_CLKIN_{MIN|MAX}_LF DFS_CLKIN_{MIN|MAX}_LF DLL_CLKOUT_{MIN|MAX}_HF DFS_CLKOUT_{MIN|MAX}_HF DLL_CLKIN_{MIN|MAX}_HF DFS_CLKIN_{MIN|MAX}_HF Data Sheet CLKOUT_FREQ_{1X|2X|DV}_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_FX_LF CLKOUT_FREQ_{1X|DV}_HF CLKOUT_FREQ_FX_HF CLKIN_FREQ_DLL_HF CLKIN_FREQ_FX_HF
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Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for QPro Virtex-II source-synchronous transmitter and receiver data-valid windows. Table 68: Duty Cycle Distortion and Clock-Tree Skew Description
Duty Cycle Distortion(1)
Symbol
TDCD_CLK0 TDCD_CLK180
Device
All All XQ2V1000 XQ2V3000 XQ2V6000
Value
140 50 90 110 550
Units
ps ps ps ps ps
Clock Tree Skew(2)
TCKSKEW
Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. TDCD_CLK0 applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O. TDCD_CLK180 applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element in the I/O. 2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 69: Package Skew Description
Package Skew(1)
Symbol
TPKGSKEW
Device/Package
XQ2V6000/CF1144
Value
90
Units
ps
Notes: 1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball (7.1ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 70: Sample Window Description
Sampling Error at Receiver Pins(1)
Symbol
TSAMP
Device
XQ2V1000 XQ2V3000 XQ2V6000
Value TBD TBD TBD
Units
ps ps ps
Notes: 1. This parameter indicates the total sampling error of QPro Virtex-II DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 and CLK180 DCM jitter - Worst-case Duty-Cycle Distortion - TDCD_CLK180 - DCM accuracy (phase offset) - DCM phase shift resolution. These measurements do not include package or clock tree skew.
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Table 71: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration Description
Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Input Switching Characteristics Standard Adjustments, page 53. No Delay Global Clock and IFF with DCM TPSDCM/TPHDCM XQ2V1000 XQ2V3000 XQ2V6000 Notes: 1. IFF = Input Flip-Flop 2. The timing values were measured using the fine-phase adjustment feature of the DCM. 3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements. TBD TBD TBD ns ns ns
Symbol
Device
Value
Units
Source Synchronous Timing Budgets
This section describes how to use the parameters provided in the Source-Synchronous Switching Characteristics section to develop system-specific timing budgets. The following analysis provides information necessary for determining QPro Virtex-II contributions to an overall system timing analysis. No assumptions are made about the effects of Inter-Symbol Interference or PCB skew.
QPro Virtex-II Transmitter Data-Valid Window (TX)
TX is the minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: TX = Data Period - [Jitter(1) + Duty Cycle Distortion(2) + TCKSKEW(3) + TPKGSKEW(4)]
Notes: 1. Jitter values and accumulation methodology to be provided in a future release of this document. The absolute period jitter values found in the DCM Timing Parameters section of the particular DCM output clock used to clock the IOB FF can be used for a best-case analysis. 2. This value depends on the clocking methodology used. See Note 1 for Table 68. 3. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. 4. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball.
QPro Virtex-II Receiver Data-Valid Window (RX)
RX is the required minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: RX = [TSAMP(1) + TCKSKEW(2) + TPKGSKEW(3)]
Notes: 1. This parameter indicates the total sampling error of QPro Virtex-II DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 and CLK180 DCM jitter in a quiet system Worst-case duty-cycle distortion DCM accuracy (phase offset) DCM phase shift resolution These measurements do not include package or clock tree skew. 2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball.
3.
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QPro Virtex-II Device/Package Combinations and Maximum I/Os Available
This section provides QPro Virtex-II Device/Package Combinations and Maximum I/Os Available and QPro Virtex-II Pin Definitions, followed by pinout tables for the following packages: * * * * FG456 Fine-Pitch BGA Package BG575 Standard BGA Package BG728 Standard BGA and CG717 Ceramic CGA Packages CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package possible for each available package. There are four package type definitions: * * * * FG denotes plastic wire-bond fine-pitch BGA (1.00 mm pitch). BG denotes plastic wire-bond ball grid array (1.27 mm pitch). CG denotes hermetic ceramic wire-bond column grid array (1.27 mm pitch). CF denotes non-hermetic ceramic flip-chip column grid array (1.00 mm pitch).
QPro Virtex-II devices are available in both wire-bond and flip-chip packages. The basic package dimensions are listed in Table 72. See Figure 52 through Figure 56 for a more complete mechanical description of each available package. Table 73 shows the maximum number of user I/Os Table 72: Package Information Package Pitch (mm) Size (mm) FG456 1.00 23 x 23 BG575 1.27 31 x 31
The number of I/Os per package include all user I/Os except the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, AND RSVD).
BG728 & CG717 1.27 35 x 35
CF1144 1.00 35 x 35
Table 73: QPro Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) Available I/Os Package FG456 BG575 BG728 CG717 CF1144 XQ2V1000 324 328 XQ2V3000 516 516 XQ2V6000 824
Notes: 1. The BG728 and CG717 packages are pinout (footprint) compatible.
QPro Virtex-II Pin Definitions
This section describes the pinouts for QPro Virtex-II devices in the following packages: * * * * FG456: wire-bond fine-pitch BGA of 1.00 mm pitch BG575 and BG728: wire-bond BGA of 1.27 mm pitch CG717: wire-bond ceramic column grid of 1.27 mm pitch CF1144: Ceramic flip-chip fine-pitch column grid of 1.00 mm pitch Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards (see the QPro Virtex-II Data Sheet). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table 74 provides definitions for all pin types. All QPro Virtex-II pinout tables are available on the distribution CD-ROM, or on the web (at http://www.xilinx.com).
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Pin Definitions
Table 74 provides a description of each pin type listed in QPro Virtex-II pinout tables. Table 74: QPro Virtex-II Pin Definitions Pin Name
User I/O Pins
Direction
Description
IO_LXXY_#
Input/Output
All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled "IO_LXXY_#", where: * IO indicates a user I/O pin. * LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. * # indicates the bank number (0 through 7).
Dual-Function Pins
IO_LXXY_#/ZZZ
The dual-function pins are labelled "IO_LXXY_#/ZZZ", where ZZZ can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 - D7, RDWR_B, or CS_B
With /ZZZ
DIN/D0, D1, D2, D3, D4, D5, D6, D7 CS_B RDWR_B BUSY/DOUT
Input/Output
In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after configuration.
Input Input Output
In SelectMAP mode, this is the active-Low Chip Select signal. This pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In SelectMAP mode, this is the active-Low Write Enable signal. This pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. This pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy chain. This pin becomes a user I/O after configuration.
INIT_B
Bidirectional (open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. This pin becomes a user I/O after configuration. These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. This pin is for the DCI voltage reference resistor of the P transistor (per bank). This pin is for the DCI voltage reference resistor of the N transistor (per bank). This is the alternative pin for the DCI voltage reference resistor of the P transistor. This is the alternative pin for the DCI voltage reference resistor of the N transistor. These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank).
GCLKx (S/P) VRP VRN ALT_VRP ALT_VRN VREF
Dedicated Pins(1)
Input/Output Input Input Input Input Input
CCLK
Input/Output
Configuration clock. Output in Master mode or Input in Slave mode.
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Table 74: QPro Virtex-II Pin Definitions (Continued) Pin Name PROG_B DONE Direction Input Input/Output Description Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. Configuration mode selection. Enable I/O pullups during configuration. Boundary Scan Clock. Boundary Scan Data Input. Boundary Scan Data Output. Boundary Scan Mode Select. Active Low power-down pin (unsupported). Driving this pin Low can adversely affect device operation and configuration. PWRDWN_B is internally pulled High, which is its default state. It does not require an external pull-up.
M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
Input Input Input Input Output Input Input
(unsupported)
Other Pins
DXN, DXP VBATT RSVD VCCO VCCAUX VCCINT GND
N/A Input N/A Input Input Input Input
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). Decryptor key memory backup supply. (Do not connect if battery is not used.) Reserved pin - do not connect. Power-supply pins for the output drivers (per bank). Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Ground.
Notes: 1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage).
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FG456 Fine-Pitch BGA Package
As shown in Table 75, the XQ2V1000 QPro Virtex-II device is available in the FG456 fine-pitch BGA package. Pins definitions are identical to the commercial grade XC2V1000-FG456. Following this table are the FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 75: FG456 BGA -- XQ2V1000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VRP_0 IO_L03P_0/VRN_0 IO_L04N_0/VREF_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L21N_0 IO_L21P_0/VREF_0 IO_L22N_0 IO_L22P_0 IO_L24N_0 IO_L24P_0 IO_L49N_0 IO_L49P_0 IO_L51N_0 IO_L51P_0/VREF_0 IO_L52N_0 IO_L52P_0 IO_L54N_0 IO_L54P_0 IO_L91N_0/VREF_0 IO_L91P_0 IO_L92N_0 IO_L92P_0 Pin Number B4 A4 C4 C5 B5 A5 D6 C6 B6 A6 E7 E8 D7 C7 B7 A7 D8 C8 B8 A8 E9 F9 D9 C9 B9 A9 E10 F10 D10 C10
Table 75: FG456 BGA -- XQ2V1000 Bank 0 0 0 0 0 0 0 0 Pin Description IO_L93N_0 IO_L93P_0 IO_L94N_0/VREF_0 IO_L94P_0 IO_L95N_0/GCLK7P IO_L95P_0/GCLK6S IO_L96N_0/GCLK5P IO_L96P_0/GCLK4S Pin Number B10 A10 E11 F11 D11 C11 B11 A11
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L96N_1/GCLK3P IO_L96P_1/GCLK2S IO_L95N_1/GCLK1P IO_L95P_1/GCLK0S IO_L94N_1 IO_L94P_1/VREF_1 IO_L93N_1 IO_L93P_1 IO_L92N_1 IO_L92P_1 IO_L91N_1 IO_L91P_1/VREF_1 IO_L54N_1 IO_L54P_1 IO_L52N_1 IO_L52P_1 IO_L51N_1/VREF_1 IO_L51P_1 IO_L49N_1 IO_L49P_1 IO_L24N_1
F12 F13 E12 D12 C12 B12 A13 B13 C13 D13 E13 E14 A14 B14 C14 D14 A15 B15 C15 D15 F14
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Pin Number E15 A16 B16 C16 D16 E16 E17 A17 B17 C17 D17 A18 B18 C18 D18 A19 B19 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L24P_2 IO_L43N_2 IO_L43P_2 IO_L45N_2 IO_L45P_2/VREF_2 IO_L46N_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L51N_2 IO_L51P_2/VREF_2 IO_L52N_2 IO_L52P_2 IO_L54N_2 IO_L54P_2 IO_L91N_2 IO_L91P_2 IO_L93N_2 IO_L93P_2/VREF_2 IO_L94N_2 IO_L94P_2 IO_L96N_2 IO_L96P_2 Pin Number G20 G21 G22 H19 H20 H21 H22 J17 J18 J19 J20 J21 J22 K17 K18 K19 K20 K21 K22 L17 L18 L19 L20 L21 L22
Table 75: FG456 BGA -- XQ2V1000 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L24P_1 IO_L22N_1 IO_L22P_1 IO_L21N_1/VREF_1 IO_L21P_1 IO_L06N_1 IO_L06P_1 IO_L05N_1 IO_L05P_1 IO_L04N_1 IO_L04P_1/VREF_1 IO_L03N_1/VRP_1 IO_L03P_1/VRN_1 IO_L02N_1 IO_L02P_1 IO_L01N_1 IO_L01P_1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2 IO_L01P_2 IO_L02N_2/VRP_2 IO_L02P_2/VRN_2 IO_L03N_2 IO_L03P_2/VREF_2 IO_L04N_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L19N_2 IO_L19P_2 IO_L21N_2 IO_L21P_2/VREF_2 IO_L22N_2 IO_L22P_2 IO_L24N_2
C21 C22 E18 F18 D21 D22 E19 E20 E21 E22 F19 F20 F21 F22 G18 H18 G19
2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3
IO_L96N_3 IO_L96P_3 IO_L94N_3 IO_L94P_3 IO_L93N_3/VREF_3 IO_L93P_3 IO_L91N_3 IO_L91P_3 IO_L54N_3
M21 M20 M19 M18 M17 N17 N22 N21 N20
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L54P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L43N_3 IO_L43P_3 IO_L24N_3 IO_L24P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L19N_3 IO_L19P_3 IO_L06N_3 IO_L06P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3/VRP_3 IO_L02P_3/VRN_3 IO_L01N_3 IO_L01P_3 Pin Number N19 N18 P18 P22 P21 P20 P19 R22 R21 R20 R19 R18 P17 T22 T21 T20 T19 U22 U21 U20 U19 T18 U18 V22 V21 V20 V19 W22 W21 Y22 Y21 W20 AA20 Table 75: FG456 BGA -- XQ2V1000 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L01N_4/DOUT AB19 4 Pin Description IO_L01P_4/INIT_B IO_L02N_4/D0 IO_L02P_4/D1 IO_L03N_4/D2/ALT_VRP_4 IO_L03P_4/D3/ALT_VRN_4 IO_L04N_4/VREF_4 IO_L04P_4 IO_L05N_4/VRP_4 IO_L05P_4/VRN_4 IO_L06N_4 IO_L06P_4 IO_L19N_4 IO_L19P_4 IO_L21N_4 IO_L21P_4/VREF_4 IO_L22N_4 IO_L22P_4 IO_L24N_4 IO_L24P_4 IO_L49N_4 IO_L49P_4 IO_L51N_4 IO_L51P_4/VREF_4 IO_L52N_4 IO_L52P_4 IO_L54N_4 IO_L54P_4 IO_L91N_4/VREF_4 IO_L91P_4 IO_L92N_4 IO_L92P_4 IO_L93N_4 IO_L93P_4 IO_L94N_4/VREF_4 IO_L94P_4 Pin Number AA19 V18 V17 W18 Y18 AA18 AB18 W17 Y17 AA17 AB17 V16 V15 W16 Y16 AA16 AB16 W15 Y15 AA15 AB15 U14 V14 W14 Y14 AA14 AB14 U13 V13 W13 Y13 AA13 AB13 U12 V12
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Pin Number W12 Y12 AA12 AB12 Bank 5 5 5 5 5 Pin Description IO_L05N_5/VRP_5 IO_L05P_5/VRN_5 IO_L04N_5 IO_L04P_5/VREF_5 IO_L03N_5/D4/ALT_VRP_5 IO_L03P_5/D5/ALT_VRN_5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number V7 V6 AB5 AA5 Y5 W5 AB4 AA4 Y4 AA3
Table 75: FG456 BGA -- XQ2V1000 Bank 4 4 4 4 Pin Description IO_L95N_4/GCLK3S IO_L95P_4/GCLK2P IO_L96N_4/GCLK1S IO_L96P_4/GCLK0P
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L96N_5/GCLK7S IO_L96P_5/GCLK6P IO_L95N_5/GCLK5S IO_L95P_5/GCLK4P IO_L94N_5 IO_L94P_5/VREF_5 IO_L93N_5 IO_L93P_5 IO_L92N_5 IO_L92P_5 IO_L91N_5 IO_L91P_5/VREF_5 IO_L54N_5 IO_L54P_5 IO_L52N_5 IO_L52P_5 IO_L51N_5/VREF_5 IO_L51P_5 IO_L49N_5 IO_L49P_5 IO_L24N_5 IO_L24P_5 IO_L22N_5 IO_L22P_5 IO_L21N_5/VREF_5 IO_L21P_5 IO_L19N_5 IO_L19P_5 IO_L06N_5 IO_L06P_5
AA11 Y11 W11 V11 U11 U10 AB10 AA10 Y10 W10 V10 V9 AB9 AA9 Y9 W9 AB8 AA8 Y8 W8 U9 V8 AB7 AA7 Y7 W7 AB6 AA6 Y6 W6
5 5 5 5 5
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
IO_L01P_6 IO_L01N_6 IO_L02P_6/VRN_6 IO_L02N_6/VRP_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L06P_6 IO_L06N_6 IO_L19P_6 IO_L19N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L24P_6 IO_L24N_6 IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6
V5 U5 Y2 Y1 V4 V3 W2 W1 U4 U3 V2 V1 U2 U1 T5 R5 T4 T3 T2 T1 R4 R3 R2 R1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 IO_L54P_6 IO_L54N_6 IO_L91P_6 IO_L91N_6 IO_L93P_6 IO_L93N_6/VREF_6 IO_L94P_6 IO_L94N_6 IO_L96P_6 IO_L96N_6 Pin Number P6 P5 P4 P3 P2 P1 N6 N5 N4 N3 N2 N1 M6 M5 M4 M3 M2 M1 Table 75: FG456 BGA -- XQ2V1000 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L96P_7 IO_L96N_7 IO_L94P_7 IO_L94N_7 IO_L93P_7/VREF_7 IO_L93N_7 IO_L91P_7 IO_L91N_7 IO_L54P_7 IO_L54N_7 IO_L52P_7 IO_L52N_7 IO_L51P_7/VREF_7 IO_L51N_7 IO_L49P_7 IO_L49N_7 L2 L3 L4 L5 K1 K2 K3 K4 L6 K6 K5 J5 J1 J2 J3 J4 0 0 0 0 0 1 1 1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 G11 G10 G9 F8 F7 G14 G13 G12 7 7 7 7 7 7 7 Pin Description IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7 IO_L45P_7/VREF_7 IO_L45N_7 IO_L43P_7 IO_L43N_7 IO_L24P_7 IO_L24N_7 IO_L22P_7 IO_L22N_7 IO_L21P_7/VREF_7 IO_L21N_7 IO_L19P_7 IO_L19N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7 IO_L03P_7/VREF_7 IO_L03N_7 IO_L02P_7/VRN_7 IO_L02N_7/VRP_7 IO_L01P_7 IO_L01N_7 Pin Number H1 H2 H3 H4 J6 H5 G1 G2 G3 G4 F1 F2 F3 F4 G5 F5 E1 E2 E3 E4 D1 D2 C1 C2 E5 E6
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Pin Number F16 F15 L16 K16 J16 H17 G17 T17 R17 P16 N16 M16 U16 U15 T14 T13 T12 U8 U7 T11 T10 T9 T6 R6 P7 N7 M7 L7 K7 J7 H6 G6 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT AB11 AA22 AA1 M22 L1 B22 B1 A12 U17 U6 T16 T15 T8 T7 R16 R7 H16 H7 G16 G15 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description DONE M0 M1 M2 HSWAP_EN TCK TDI TDO TMS PWRDWN_B DXN DXP VBATT RSVD Pin Number AB20 AB2 W3 AB3 B3 C19 D3 D20 B20 AB21 D5 A3 A21 A20
Table 75: FG456 BGA -- XQ2V1000 Bank 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 Pin Description VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7
NA NA
CCLK PROG_B
Y19 A2
NA NA
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 75: FG456 BGA -- XQ2V1000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number G8 G7 F17 F6 AB22 AB1 AA21 AA2 Y20 Y3 W19 W4 P14 P13 P12 P11 P10 P9 N14 N13 N12 N11 N10 N9 M14 M13 M12 M11 M10 M9 L14 L13 L12 L11 L10 Table 75: FG456 BGA -- XQ2V1000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L9 K14 K13 K12 K11 K10 K9 J14 J13 J12 J11 J10 J9 D19 D4 C20 C3 B21 B2 A22 A1
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QPro Virtex-II 1.5V Military QML Platform FPGAs
FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 52: FG456 Fine-Pitch BGA Package Specifications
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QPro Virtex-II 1.5V Military QML Platform FPGAs
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BG575 Standard BGA Package
As shown in Table 76, the XQ2V1000 QPro Virtex-II device is available in the BG575 BGA package. Following this table are the BG575 Standard BGA Package Specifications (1.27mm pitch).
Table 76: BG575 BGA -- XQ2V1000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VRP_0 IO_L03P_0/VRN_0 IO_L04N_0/VREF_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L19N_0 IO_L19P_0 IO_L21N_0 IO_L21P_0/VREF_0 IO_L22N_0 IO_L22P_0 IO_L24N_0 IO_L24P_0 IO_L49N_0 IO_L49P_0 IO_L51N_0 IO_L51P_0/VREF_0 IO_L52N_0 IO_L52P_0 IO_L54N_0 IO_L54P_0 IO_L67N_0 IO_L67P_0 IO_L69N_0 Pin Number A3 A4 D5 C5 E6 D6 F7 E7 G8 H9 A5 A6 B5 B6 D7 C7 F8 E8 G9 F9 G10 H10 B7 B8 D8 C8 E9 D9 A8 A9 C9
Table 76: BG575 BGA -- XQ2V1000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L69P_0/VREF_0 IO_L70N_0 IO_L70P_0 IO_L72N_0 IO_L72P_0 IO_L73N_0 IO_L73P_0 IO_L91N_0/VREF_0 IO_L91P_0 IO_L92N_0 IO_L92P_0 IO_L93N_0 IO_L93P_0 IO_L94N_0/VREF_0 IO_L94P_0 IO_L95N_0/GCLK7P IO_L95P_0/GCLK6S IO_L96N_0/GCLK5P IO_L96P_0/GCLK4S Pin Number B9 F10 E10 A10 A11 C10 B10 D11 C11 G11 E11 C12 B12 E12 D12 G12 F12 H11 H12
1 1 1 1 1 1 1 1 1 1 1
IO_L96N_1/GCLK3P IO_L96P_1/GCLK2S IO_L95N_1/GCLK1P IO_L95P_1/GCLK0S IO_L94N_1 IO_L94P_1/VREF_1 IO_L93N_1 IO_L93P_1 IO_L92N_1 IO_L92P_1 IO_L91N_1
A13 A14 B13 C13 D13 E13 F13 G13 H13 H14 C14
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Pin Number D14 E14 G14 A15 A16 B15 C15 E15 F15 G15 H15 B16 C16 D16 E16 F16 G16 A17 A19 B17 B18 C17 D17 F17 E17 A20 A21 B19 B20 C18 D18 C20 D20 D19 E19 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L01N_2 IO_L01P_2 IO_L02N_2/VRP_2 IO_L02P_2/VRN_2 IO_L03N_2 IO_L03P_2/VREF_2 IO_L04N_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L19N_2 IO_L19P_2 IO_L21N_2 IO_L21P_2/VREF_2 IO_L22N_2 IO_L22P_2 IO_L24N_2 IO_L24P_2 IO_L43N_2 IO_L43P_2 IO_L45N_2 IO_L45P_2/VREF_2 IO_L46N_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L51N_2 IO_L51P_2/VREF_2 D22 D23 E21 E22 F21 F20 G20 G19 H18 J17 D24 E23 E24 F24 F23 G23 G21 G22 H19 H20 J18 J19 K17 K18 H23 H24 H21 H22 J24 K24 Bank 1 1 1 1 Pin Description IO_L02N_1 IO_L02P_1 IO_L01N_1 IO_L01P_1 Pin Number E18 F18 H16 G17
Table 76: BG575 BGA -- XQ2V1000 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L91P_1/VREF_1 IO_L73N_1 IO_L73P_1 IO_L72N_1 IO_L72P_1 IO_L70N_1 IO_L70P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L67N_1 IO_L67P_1 IO_L54N_1 IO_L54P_1 IO_L52N_1 IO_L52P_1 IO_L51N_1/VREF_1 IO_L51P_1 IO_L49N_1 IO_L49P_1 IO_L24N_1 IO_L24P_1 IO_L22N_1 IO_L22P_1 IO_L21N_1/VREF_1 IO_L21P_1 IO_L19N_1 IO_L19P_1 IO_L06N_1 IO_L06P_1 IO_L05N_1 IO_L05P_1 IO_L04N_1 IO_L04P_1/VREF_1 IO_L03N_1/VRP_1 IO_L03P_1/VRN_1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L52N_2 IO_L52P_2 IO_L54N_2 IO_L54P_2 IO_L67N_2 IO_L67P_2 IO_L69N_2 IO_L69P_2/VREF_2 IO_L70N_2 IO_L70P_2 IO_L72N_2 IO_L72P_2 IO_L73N_2 IO_L73P_2 IO_L91N_2 IO_L91P_2 IO_L93N_2 IO_L93P_2/VREF_2 IO_L94N_2 IO_L94P_2 IO_L96N_2 IO_L96P_2 Pin Number J22 J23 J20 J21 K19 K20 L17 L18 K23 L24 K22 L22 L21 L20 M23 N24 M21 M22 M19 M20 M17 M18 Table 76: BG575 BGA -- XQ2V1000 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L96N_3 IO_L96P_3 IO_L94N_3 IO_L94P_3 IO_L93N_3/VREF_3 IO_L93P_3 IO_L91N_3 IO_L91P_3 IO_L73N_3 IO_L73P_3 IO_L72N_3 IO_L72P_3 N23 N22 N20 N21 N19 N18 N17 P17 P24 R24 R23 R22 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L70N_3 IO_L70P_3 IO_L69N_3/VREF_3 IO_L69P_3 IO_L67N_3 IO_L67P_3 IO_L54N_3 IO_L54P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L43N_3 IO_L43P_3 IO_L24N_3 IO_L24P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L19N_3 IO_L19P_3 IO_L06N_3 IO_L06P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 Pin Number P22 P21 P20 P18 T24 U24 T23 T22 T21 T20 R20 R19 W24 W23 U23 V23 U22 U21 V22 V21 U19 U20 T19 T18 R18 R17 Y24 Y23 AA24 AB24 AA23 AA22 Y22 Y21 W21
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Pin Number W20 V20 V19 U18 T17 Bank 4 4 4 4 4 4 Pin Description IO_L67P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L70N_4 IO_L70P_4 IO_L72N_4 IO_L72P_4 IO_L73N_4 IO_L73P_4 IO_L91N_4/VREF_4 IO_L91P_4 IO_L92N_4 IO_L92P_4 IO_L93N_4 IO_L93P_4 IO_L94N_4/VREF_4 IO_L94P_4 IO_L95N_4/GCLK3S IO_L95P_4/GCLK2P IO_L96N_4/GCLK1S IO_L96P_4/GCLK0P Pin Number AA16 W15 Y15 U15 V15 AD15 AD14 AB15 AC15 AA14 AB14 V14 Y14 AB13 AC13 Y13 AA13 V13 W13 U14 U13
Table 76: BG575 BGA -- XQ2V1000 Bank 3 3 3 3 3 Pin Description IO_L03P_3 IO_L02N_3/VRP_3 IO_L02P_3/VRN_3 IO_L01N_3 IO_L01P_3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
IO_L01N_4/DOUT IO_L01P_4/INIT_B IO_L02N_4/D0 IO_L02P_4/D1 IO_L03N_4/D2/ALT_VRP_4 IO_L03P_4/D3/ALT_VRN_4 IO_L04N_4/VREF_4 IO_L04P_4 IO_L05N_4/VRP_4 IO_L05P_4/VRN_4 IO_L06N_4 IO_L06P_4 IO_L19N_4 IO_L19P_4 IO_L21N_4 IO_L21P_4/VREF_4 IO_L22N_4 IO_L22P_4 IO_L24N_4 IO_L24P_4 IO_L49N_4 IO_L49P_4 IO_L51N_4 IO_L51P_4/VREF_4 IO_L52N_4 IO_L52P_4 IO_L54N_4 IO_L54P_4 IO_L67N_4
AD22 AD21 AA20 AB20 Y19 AA19 W18 Y18 U16 V17 AD20 AD19 AC20 AC19 AA18 AB18 AC18 AC17 AA17 AB17 Y17 W17 V16 W16 AD17 AD16 AB16 AC16 Y16
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L96N_5/GCLK7S IO_L96P_5/GCLK6P IO_L95N_5/GCLK5S IO_L95P_5/GCLK4P IO_L94N_5 IO_L94P_5/VREF_5 IO_L93N_5 IO_L93P_5 IO_L92N_5 IO_L92P_5 IO_L91N_5 IO_L91P_5/VREF_5 IO_L73N_5
AD12 AD11 AC12 AB12 AA12 Y12 W12 V12 U12 U11 AB11 AA11 Y11
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L73P_5 IO_L72N_5 IO_L72P_5 IO_L70N_5 IO_L70P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L67N_5 IO_L67P_5 IO_L54N_5 IO_L54P_5 IO_L52N_5 IO_L52P_5 IO_L51N_5/VREF_5 IO_L51P_5 IO_L49N_5 IO_L49P_5 IO_L24N_5 IO_L24P_5 IO_L22N_5 IO_L22P_5 IO_L21N_5/VREF_5 IO_L21P_5 IO_L19N_5 IO_L19P_5 IO_L06N_5 IO_L06P_5 IO_L05N_5/VRP_5 IO_L05P_5/VRN_5 IO_L04N_5 IO_L04P_5/VREF_5 IO_L03N_5/D4/ALT_VRP_5 IO_L03P_5/D5/ALT_VRN_5 IO_L02N_5/D6 IO_L02P_5/D7 Pin Number V11 AD10 AD9 AC10 AB10 Y10 W10 V10 U10 AC9 AB9 AA9 Y9 W9 V9 AD8 AD6 AC8 AC7 AB8 AA8 W8 Y8 AD5 AD4 AC6 AC5 AB7 AA7 AB5 AA5 AA6 Y6 Y7 W7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L01P_6 IO_L01N_6 IO_L02P_6/VRN_6 IO_L02N_6/VRP_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L06P_6 IO_L06N_6 IO_L19P_6 IO_L19N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L24P_6 IO_L24N_6 IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 AB2 AB1 AA3 AA2 Y4 Y3 W4 W5 V5 V6 U7 T8 AA1 Y2 Y1 W1 W2 V2 V4 V3 U6 U5 T7 T6 R8 R7 U2 U1 U4 U3 T1 R1 Table 76: BG575 BGA -- XQ2V1000 Bank 5 5 Pin Description IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number V8 U9
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Pin Number T3 T2 T5 T4 R6 R5 P8 P7 R2 P1 R3 P3 P5 P4 N4 N3 N6 N5 N8 N7 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L69P_7/VREF_7 IO_L69N_7 IO_L67P_7 IO_L67N_7 IO_L54P_7 IO_L54N_7 IO_L52P_7 IO_L52N_7 IO_L51P_7/VREF_7 IO_L51N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7 IO_L45P_7/VREF_7 IO_L45N_7 IO_L43P_7 IO_L43N_7 IO_L24P_7 IO_L24N_7 IO_L22P_7 IO_L22N_7 IO_L21P_7/VREF_7 IO_L21N_7 IO_L19P_7 IO_L19N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7 IO_L03P_7/VREF_7 IO_L03N_7 IO_L02P_7/VRN_7 Pin Number L3 L4 L5 L7 J1 H1 J2 J3 J4 J5 K5 K6 F1 F2 H2 G2 H3 H4 G3 G4 H5 H6 J6 J7 K7 K8 E1 E2 D2 D3 E3 E4 F4 F5 G5
Table 76: BG575 BGA -- XQ2V1000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L54P_6 IO_L54N_6 IO_L67P_6 IO_L67N_6 IO_L69P_6 IO_L69N_6/VREF_6 IO_L70P_6 IO_L70N_6 IO_L72P_6 IO_L72N_6 IO_L73P_6 IO_L73N_6 IO_L91P_6 IO_L91N_6 IO_L93P_6 IO_L93N_6/VREF_6 IO_L94P_6 IO_L94N_6 IO_L96P_6 IO_L96N_6
7 7 7 7 7 7 7 7 7 7 7 7 7 7
IO_L96P_7 IO_L96N_7 IO_L94P_7 IO_L94N_7 IO_L93P_7/VREF_7 IO_L93N_7 IO_L91P_7 IO_L91N_7 IO_L73P_7 IO_L73N_7 IO_L72P_7 IO_L72N_7 IO_L70P_7 IO_L70N_7
N2 M1 M2 M3 M4 M5 M6 M7 M8 L8 L1 K1 K2 K3
7 7 7 7 7 7 7 7 7 7 7 7 7 7
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Bank 7 7 7 Pin Description IO_L02N_7/VRP_7 IO_L01P_7 IO_L01N_7 Pin Number G6 H7 J8 Table 76: BG575 BGA -- XQ2V1000 Bank 5 5 5 5 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 J12 J11 J10 F11 C6 B11 J15 J14 J13 F14 C19 B14 M16 L23 L19 L16 K16 F22 W22 R16 P23 P19 P16 N16 AC14 AB19 W14 T15 T14 T13 AC11 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA CCLK PROG_B DONE M0 M1 M2 HSWAP_EN TCK TDI TDO TMS PWRDWN_B DXN DXP VBATT RSVD AB23 C1 AB21 AC4 AB4 AD3 C2 C23 D1 C24 C21 AC21 B4 C4 B21 A22 5 6 6 6 6 6 6 7 7 7 7 7 7 Pin Description VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number AB6 W11 T12 T11 T10 W3 R9 P9 P6 P2 N9 M9 L9 L6 L2 K9 F3
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Pin Number Bank NA Pin Description VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number H17 H8 AD24 AD23 AD18 AD7 AD2 AD1 AC24 AC23 AC2 AC1 AB22 AB3 AA21 AA15 AA10 AA4 Y20 Y5 W19 W6 V24 V18 V7 V1 R21 R4 P14 P13 P12 P11 N14 N13 N12
Table 76: BG575 BGA -- XQ2V1000 Bank Pin Description
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
AD13 AC22 AC3 N1 M24 B22 B3 A12 U17 U8 T16 T9 R15 R14 R13 R12 R11 R10 P15 P10 N15 N10 M15 M10 L15 L10 K15 K14 K13 K12 K11 K10 J16 J9
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 76: BG575 BGA -- XQ2V1000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number N11 M14 M13 M12 M11 L14 L13 L12 L11 K21 K4 G24 G18 G7 G1 F19 F6 E20 E5 D21 D15 D10 D4 C22 C3 B24 B23 B2 B1 A24 A23 A18 A7 A2
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QPro Virtex-II 1.5V Military QML Platform FPGAs
BG575 Standard BGA Package Specifications (1.27mm pitch)
Figure 53: BG575 Standard BGA Package Specifications
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QPro Virtex-II 1.5V Military QML Platform FPGAs
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BG728 Standard BGA and CG717 Ceramic CGA Packages
As shown in Table 78, the XQ2V3000 QPro Virtex-II device is available in the BG728 BGA and CG717 CGA packages. The CG717 has identical pinout as the BG728 (except for those pins listed as Removed1) and footprint compatibility. A summary of the removed pins is shown in Table 77. Following this table are the BG728 Standard BGA Package Specifications (1.27mm pitch) and the CG717 Ceramic Column Grid Array (CGA) Package Specifications (1.27mm pitch) The CG717 has 11 fewer GND pins than the BG728. The BG728 GND pin numbers missing on the CG717 are shown in Table 77. Table 77: BG728 GND Pins not available on the CG7171 BG728 GND Pin Numbers A2 B1 A26
1.
A27 B27 AF1
AG1 AG2 AF27
AG26 AG27
Physical pin does not exist for CG717 package.
.
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VRP_0 IO_L03P_0/VRN_0 IO_L04N_0/VREF_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L19N_0 IO_L19P_0 IO_L21N_0 IO_L21P_0/VREF_0 IO_L22N_0 IO_L22P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0 IO_L25P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L28N_0 Pin Number B3 A3 B4 A4 C5 C6 B5 A5 E6 D6 B6 A6 E7 D8 F8 E8 C7 C8 B7 A7 H9 J9 F9 G9 E9
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L28P_0 IO_L30N_0 IO_L30P_0 IO_L49N_0 IO_L49P_0 IO_L51N_0 IO_L51P_0/VREF_0 IO_L52N_0 IO_L52P_0 IO_L54N_0 IO_L54P_0 IO_L67N_0 IO_L67P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L70N_0 IO_L70P_0 IO_L72N_0 IO_L72P_0 IO_L73N_0 IO_L73P_0 IO_L75N_0 IO_L75P_0/VREF_0 IO_L76N_0 IO_L76P_0 Pin Number D9 C9 B9 A8 A9 G10 H10 F10 E10 D10 C10 B10 A10 G11 H11 F11 F12 D11 C11 B11 A11 H12 J12 E12 D12
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L72N_1 IO_L72P_1 IO_L70N_1 IO_L70P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L67N_1 IO_L67P_1 IO_L54N_1 IO_L54P_1 IO_L52N_1 IO_L52P_1 IO_L51N_1/VREF_1 IO_L51P_1 IO_L49N_1 IO_L49P_1 IO_L30N_1 IO_L30P_1 IO_L28N_1 IO_L28P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L25N_1 IO_L25P_1 IO_L24N_1 IO_L24P_1 IO_L22N_1 IO_L22P_1 IO_L21N_1/VREF_1 IO_L21P_1 IO_L19N_1 IO_L19P_1 IO_L06N_1 IO_L06P_1 IO_L05N_1 Pin Number A17 B17 C17 D17 G18 G17 A18 B18 C18 D18 E18 F18 H19 H18 A19 A20 B19 C19 D19 E19 F19 G19 J19 J20 C20 C21 D20 E21 E20 F20 A21 B21 A22 B22 C22
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L78N_0 IO_L78P_0 IO_L91N_0/VREF_0 IO_L91P_0 IO_L92N_0 IO_L92P_0 IO_L93N_0 IO_L93P_0 IO_L94N_0/VREF_0 IO_L94P_0 IO_L95N_0/GCLK7P IO_L95P_0/GCLK6S IO_L96N_0/GCLK5P IO_L96P_0/GCLK4S Pin Number B12 A12 J13 H13 G13 F13 E13 D13 B13 A13 C13 C14 F14 E14
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L96N_1/GCLK3P IO_L96P_1/GCLK2S IO_L95N_1/GCLK1P IO_L95P_1/GCLK0S IO_L94N_1 IO_L94P_1/VREF_1 IO_L93N_1 IO_L93P_1 IO_L92N_1 IO_L92P_1 IO_L91N_1 IO_L91P_1/VREF_1 IO_L78N_1 IO_L78P_1 IO_L76N_1 IO_L76P_1 IO_L75N_1/VREF_1 IO_L75P_1 IO_L73N_1 IO_L73P_1
G14 H14 A15 B15 C15 D15 E15 F15 G15 H15 J15 J16 A16 B16 D16 E16 F16 F17 H16 H17
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 1 1 1 1 1 1 1 1 1 Pin Description IO_L05P_1 IO_L04N_1 IO_L04P_1/VREF_1 IO_L03N_1/VRP_1 IO_L03P_1/VRN_1 IO_L02N_1 IO_L02P_1 IO_L01N_1 IO_L01P_1 Pin Number C23 D22 E22 A23 B23 A24 B24 A25 B25 Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L01N_2 IO_L01P_2 IO_L02N_2/VRP_2 IO_L02P_2/VRN_2 IO_L03N_2 IO_L03P_2/VREF_2 IO_L04N_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L19N_2 IO_L19P_2 IO_L21N_2 IO_L21P_2/VREF_2 IO_L22N_2 IO_L22P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L27N_2 IO_L27P_2/VREF_2 IO_L28N_2 IO_L28P_2 IO_L30N_2 C27 D27 D25 D26 E24 E25 E26 E27 F23 F24 F25 F26 F27 G27 G23 H23 G25 G26 H21 J21 H22 J22 H24 H25 H27 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L30P_2 IO_L43N_2 IO_L43P_2 IO_L45N_2 IO_L45P_2/VREF_2 IO_L46N_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L51N_2 IO_L51P_2/VREF_2 IO_L52N_2 IO_L52P_2 IO_L54N_2 IO_L54P_2 IO_L67N_2 IO_L67P_2 IO_L69N_2 IO_L69P_2/VREF_2 IO_L70N_2 IO_L70P_2 IO_L72N_2 IO_L72P_2 IO_L73N_2 IO_L73P_2 IO_L75N_2 IO_L75P_2/VREF_2 IO_L76N_2 IO_L76P_2 IO_L78N_2 IO_L78P_2 IO_L91N_2 IO_L91P_2 Pin Number J27 J23 J24 J25 J26 K20 K21 K22 K23 K24 K25 K26 K27 L20 M20 L21 L22 L24 L25 L26 L27 M19 N19 M22 M23 M24 N24 M26 M27 N20 N21 N22 N23 N25 P25
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 3 3 3 3 3 3 3 Pin Description IO_L51N_3/VREF_3 IO_L51P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L43N_3 IO_L43P_3 IO_L28N_3 IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L19N_3 IO_L19P_3 IO_L06N_3 IO_L06P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3/VRP_3 IO_L02P_3/VRN_3 IO_L01N_3 Pin Number V22 W22 V21 V20 W27 Y27 W26 W25 W24 W23 W21 W20 W19 Y19 Y25 Y24 Y23 AA23 Y22 Y21 AA27 AB27 AA26 AA25 AB26 AB25 AB24 AB23 AC27 AC26 AC25 AC24 AD27 AE27 AD26
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 2 2 2 2 2 2 Pin Description IO_L93N_2 IO_L93P_2/VREF_2 IO_L94N_2 IO_L94P_2 IO_L96N_2 IO_L96P_2 Pin Number N26 N27 P20 P21 P22 P23
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L96N_3 IO_L96P_3 IO_L94N_3 IO_L94P_3 IO_L93N_3/VREF_3 IO_L93P_3 IO_L91N_3 IO_L91P_3 IO_L78N_3 IO_L78P_3 IO_L76N_3 IO_L76P_3 IO_L75N_3/VREF_3 IO_L75P_3 IO_L73N_3 IO_L73P_3 IO_L72N_3 IO_L72P_3 IO_L70N_3 IO_L70P_3 IO_L69N_3/VREF_3 IO_L69P_3 IO_L67N_3 IO_L67P_3 IO_L54N_3 IO_L54P_3 IO_L52N_3 IO_L52P_3
R27 R26 R25 R24 R23 T23 R22 R21 R20 R19 T27 T26 T24 U24 T22 U22 T20 T19 U27 U26 U25 V25 U21 U20 V27 V26 V24 V23
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 3 Pin Description IO_L01P_3 Pin Number AD25 Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IO_L01N_4/DOUT IO_L01P_4/INIT_B IO_L02N_4/D0 IO_L02P_4/D1 IO_L03N_4/D2/ALT_VRP_4 IO_L03P_4/D3/ALT_VRN_4 IO_L04N_4/VREF_4 IO_L04P_4 IO_L05N_4/VRP_4 IO_L05P_4/VRN_4 IO_L06N_4 IO_L06P_4 IO_L19N_4 IO_L19P_4 IO_L21N_4 IO_L21P_4/VREF_4 IO_L22N_4 IO_L22P_4 IO_L24N_4 IO_L24P_4 IO_L25N_4 IO_L25P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L28N_4 IO_L28P_4 IO_L30N_4 IO_L30P_4 IO_L49N_4 IO_L49P_4 IO_L51N_4 IO_L51P_4/VREF_4 IO_L52N_4 AF25 AG25 AF24 AG24 AD23 AE23 AF23 AG23 AD22 AE22 AF22 AG22 AC21 AB21 AE21 AE20 AF21 AG21 AB20 AA20 AC20 AD20 AG20 AG19 AB19 AA19 AC19 AD19 AE19 AF19 AA18 Y18 AB18 5 5 5 IO_L96N_5/GCLK7S IO_L96P_5/GCLK6P IO_L95N_5/GCLK5S AC14 AB14 AG13 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L52P_4 IO_L54N_4 IO_L54P_4 IO_L67N_4 IO_L67P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L70N_4 IO_L70P_4 IO_L72N_4 IO_L72P_4 IO_L73N_4 IO_L73P_4 IO_L75N_4 IO_L75P_4/VREF_4 IO_L76N_4 IO_L76P_4 IO_L78N_4 IO_L78P_4 IO_L91N_4/VREF_4 IO_L91P_4 IO_L92N_4 IO_L92P_4 IO_L93N_4 IO_L93P_4 IO_L94N_4/VREF_4 IO_L94P_4 IO_L95N_4/GCLK3S IO_L95P_4/GCLK2P IO_L96N_4/GCLK1S IO_L96P_4/GCLK0P Pin Number AC18 AD18 AE18 AF18 AG18 AA17 Y17 AB17 AB16 AD17 AE17 AF17 AG17 Y16 W16 AC16 AD16 AF16 AG16 W15 Y15 AB15 AA15 AC15 AD15 AE15 AE14 AF15 AG15 Y14 AA14
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L28N_5 IO_L28P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L25N_5 IO_L25P_5 IO_L24N_5 IO_L24P_5 IO_L22N_5 IO_L22P_5 IO_L21N_5/VREF_5 IO_L21P_5 IO_L19N_5 IO_L19P_5 IO_L06N_5 IO_L06P_5 IO_L05N_5/VRP_5 IO_L05P_5/VRN_5 IO_L04N_5 IO_L04P_5/VREF_5 IO_L03N_5/D4/ALT_VRP_5 IO_L03P_5/D5/ALT_VRN_5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number AD9 AC9 AB9 AA9 AE8 AE7 AD8 AC8 AB8 AA8 AG7 AF7 AC7 AB7 AG6 AF6 AE6 AD6 AG5 AF5 AE5 AD5 AG4 AF4 AG3 AF3
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L95P_5/GCLK4P IO_L94N_5 IO_L94P_5/VREF_5 IO_L93N_5 IO_L93P_5 IO_L92N_5 IO_L92P_5 IO_L91N_5 IO_L91P_5/VREF_5 IO_L78N_5 IO_L78P_5 IO_L76N_5 IO_L76P_5 IO_L75N_5/VREF_5 IO_L75P_5 IO_L73N_5 IO_L73P_5 IO_L72N_5 IO_L72P_5 IO_L70N_5 IO_L70P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L67N_5 IO_L67P_5 IO_L54N_5 IO_L54P_5 IO_L52N_5 IO_L52P_5 IO_L51N_5/VREF_5 IO_L51P_5 IO_L49N_5 IO_L49P_5 IO_L30N_5 IO_L30P_5 Pin Number AF13 AE13 AD13 AC13 AB13 AA13 Y13 W13 W12 AG12 AF12 AD12 AC12 AB12 AB11 Y12 Y11 AG11 AF11 AE11 AD11 AA10 AA11 AG10 AF10 AE10 AD10 AC10 AB10 Y9 Y10 AG9 AG8 AF9 AE9
6 6 6 6 6 6 6 6
IO_L01P_6 IO_L01N_6 IO_L02P_6/VRN_6 IO_L02N_6/VRP_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6
AE1 AD1 AD3 AD2 AC4 AC3 AC2 AC1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L06P_6 IO_L06N_6 IO_L19P_6 IO_L19N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 IO_L25N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 IO_L54P_6 IO_L54N_6 IO_L67P_6 IO_L67N_6 IO_L69P_6 Pin Number AB5 AB4 AB3 AB2 AB1 AA1 AA5 AA6 AA3 AA2 Y5 Y6 Y4 Y3 Y1 W1 W8 W9 W6 W7 W5 W4 W3 W2 V7 V8 V5 V6 V4 V3 V2 V1 U8 T8 U6 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L96P_7 IO_L96N_7 IO_L94P_7 IO_L94N_7 IO_L93P_7/VREF_7 IO_L93N_7 IO_L91P_7 IO_L91N_7 IO_L78P_7 IO_L78N_7 IO_L76P_7 IO_L76N_7 IO_L75P_7/VREF_7 P5 P6 P7 P8 N1 N2 N3 N4 N6 N7 N9 N8 N5 Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L69N_6/VREF_6 IO_L70P_6 IO_L70N_6 IO_L72P_6 IO_L72N_6 IO_L73P_6 IO_L73N_6 IO_L75P_6 IO_L75N_6/VREF_6 IO_L76P_6 IO_L76N_6 IO_L78P_6 IO_L78N_6 IO_L91P_6 IO_L91N_6 IO_L93P_6 IO_L93N_6/VREF_6 IO_L94P_6 IO_L94N_6 IO_L96P_6 IO_L96N_6 Pin Number U7 U4 U3 U2 U1 T9 R9 T5 T6 T4 R4 T2 T1 R7 R8 R5 R6 R3 P3 R2 R1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L24P_7 IO_L24N_7 IO_L22P_7 IO_L22N_7 IO_L21P_7/VREF_7 IO_L21N_7 IO_L19P_7 IO_L19N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7 IO_L03P_7/VREF_7 IO_L03N_7 IO_L02P_7/VRN_7 IO_L02N_7/VRP_7 IO_L01P_7 IO_L01N_7 Pin Number G1 F1 G2 G3 F2 F3 G5 G6 F4 F5 E1 E2 D1 C1 E3 E4 D2 D3
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L75N_7 IO_L73P_7 IO_L73N_7 IO_L72P_7 IO_L72N_7 IO_L70P_7 IO_L70N_7 IO_L69P_7/VREF_7 IO_L69N_7 IO_L67P_7 IO_L67N_7 IO_L54P_7 IO_L54N_7 IO_L52P_7 IO_L52N_7 IO_L51P_7/VREF_7 IO_L51N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7 IO_L45P_7/VREF_7 IO_L45N_7 IO_L43P_7 IO_L43N_7 IO_L30P_7 IO_L30N_7 IO_L28P_7 IO_L28N_7 IO_L27P_7/VREF_7 IO_L27N_7 IO_L25P_7 IO_L25N_7 Pin Number M6 M1 M2 M4 M5 M8 M9 L1 L2 L3 L4 K1 K2 K4 K5 L6 L7 K6 K7 L8 K8 J1 H1 J2 J3 K3 J4 H3 H4 J5 J6 H5 H6 J7 J8
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1
K13 K12 K11 J11 J10 G12 D7 C12 K17 K16 K15 J18 J17 G16 D21 C16
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 Pin Description VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 Pin Number N18 M25 M21 M18 L19 L18 K19 G24 AA24 V19 U19 U18 T25 T21 T18 R18 AE16 AD21 AA16 W18 W17 V17 V16 V15 AE12 AD7 AA12 W11 W10 V13 V12 V11 AA4 V9 U10 NA NA NA NA VCCAUX VCCAUX VCCAUX VCCAUX AF14 AE26 AE2 P26 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA CCLK PROG_B DONE M0 M1 M2 HSWAP_EN TCK TDI TDO TMS PWRDWN_B DXN DXP VBATT RSVD AA22 C4 AC22 AC6 Y7 AE4 D5 G20 H7 G22 F21 AE24 G8 F7 D23 C24 Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank 6 6 6 6 6 7 7 7 7 7 7 7 7 Pin Description VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number U9 T10 T7 T3 R10 M10 M7 M3 L10 L9 K9 G4 N10
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description VCCINT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number K10 AG271 AG261 AG14 AG21 AG11 AF271 AF26 AF20 AF8 AF2 AF11 AE25 AE3 AD24 AD14 AD4 AC23 AC17 AC11 AC5 AB22 AB6 AA21 AA7 Y26 Y20 Y8 Y2 W14 U23 U5 T16 T15 T14
Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number P2 C26 C2 B14 V18 V14 V10 U17 U16 U15 U14 U13 U12 U11 T17 T11 R17 R11 P18 P17 P11 P10 N17 N11 M17 M11 L17 L16 L15 L14 L13 L12 L11 K18 K14
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number T13 T12 R16 R15 R14 R13 R12 P27 P24 P19 P16 P15 P14 P13 P12 P9 P4 P1 N16 N15 N14 N13 N12 M16 M15 M14 M13 M12 L23 L5 J14 H26 H20 H8 H2 Table 78: BG728 BGA and CG717 CGA-- XQ2V3000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number G21 G7 F22 F6 E23 E17 E11 E5 D24 D14 D4 C25 C3 B271 B26 B20 B8 B2 B11 A271 A261 A14 A2
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QPro Virtex-II 1.5V Military QML Platform FPGAs
BG728 Standard BGA Package Specifications (1.27mm pitch)
Figure 54: BG728 Standard BGA Package Specifications
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QPro Virtex-II 1.5V Military QML Platform FPGAs
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CG717 Ceramic Column Grid Array (CGA) Package Specifications (1.27mm pitch)
Figure 55: CG717 Ceramic CGA Package Specifications
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QPro Virtex-II 1.5V Military QML Platform FPGAs
CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package
As shown in Table 80, The XQ2V6000 QPro Virtex-II device is available in the CF1144 flip-chip fine-pitch CGA package. Pins for this package are the same as the FF1152, except for those pins shown in Table 79 have been removed. Following this table are the CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package Specifications (1.00mm pitch). The CF1144 has eight fewer GND pins than the FF1152. The FF1152 GND Pin numbers missing on the CF1144 are shown in Table 79. Table 79: FF1152 GND Pins not available on the CF1144 FF1152 GND Pin Numbers A2 B1
1.
A33 B34
AN1 AP2
AN34 AP33
Physical pin does not exist for CF1144 package
Table 80: CF1144 CGA -- XQ2V6000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VRP_0 IO_L03P_0/VRN_0 IO_L04N_0/VREF_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0/VREF_0 IO_L22N_0 IO_L22P_0 IO_L23N_0 IO_L23P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0 IO_L25P_0 Pin Number D29 C29 H26 G26 E28 E27 F25 F26 H25 H24 E26 F27 B32 C33 J24 J23 C27 C28 B30 B31 K23 K22 C26 D27 A30 A31
Table 80: CF1144 CGA -- XQ2V6000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L49N_0 IO_L49P_0 IO_L50N_0 IO_L50P_0 IO_L51N_0 IO_L51P_0/VREF_0 IO_L52N_0 IO_L52P_0 IO_L53N_0 IO_L53P_0 IO_L54N_0 IO_L54P_0 IO_L60N_0 IO_L60P_0 IO_L67N_0 IO_L67P_0 Pin Number G24 G25 E25 E24 D25 D26 H23 H22 F23 F24 B28 B29 J22 J21 A28 A29 A26 B27 C24 D24 D22 D23 B25 B26 B23 B24
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L70N_0 IO_L70P_0 IO_L71N_0 IO_L71P_0 IO_L72N_0 IO_L72P_0 IO_L73N_0 IO_L73P_0 IO_L74N_0 IO_L74P_0 IO_L75N_0 IO_L75P_0/VREF_0 IO_L76N_0 IO_L76P_0 IO_L77N_0 IO_L77P_0 IO_L78N_0 IO_L78P_0 IO_L79N_0 IO_L79P_0 IO_L80N_0 IO_L80P_0 IO_L81N_0 IO_L81P_0/VREF_0 IO_L82N_0 IO_L82P_0 IO_L83N_0 IO_L83P_0 IO_L84N_0 IO_L84P_0 IO_L91N_0/VREF_0 Pin Number G22 G23 F22 F21 A23 A24 K21 K20 C22 C23 E21 E22 H21 H20 G20 F20 B21 B22 J20 K19 D20 D21 A21 A22 L19 L18 B19 A20 A18 B18 H19 H18 C20 C21 D19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IO_L96N_1/GCLK3P IO_L96P_1/GCLK2S IO_L95N_1/GCLK1P IO_L95P_1/GCLK0S IO_L94N_1 IO_L94P_1/VREF_1 IO_L93N_1 IO_L93P_1 IO_L92N_1 IO_L92P_1 IO_L91N_1 IO_L91P_1/VREF_1 IO_L84N_1 IO_L84P_1 IO_L83N_1 IO_L83P_1 IO_L82N_1 IO_L82P_1 IO_L81N_1/VREF_1 IO_L81P_1 IO_L80N_1 IO_L80P_1 IO_L79N_1 E17 E16 H17 H16 D17 D16 F16 F17 G16 G17 C16 C15 D14 D15 J17 K17 B17 A17 A15 B16 L17 L16 A13 Table 80: CF1144 CGA -- XQ2V6000 Bank 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L91P_0 IO_L92N_0 IO_L92P_0 IO_L93N_0 IO_L93P_0 IO_L94N_0/VREF_0 IO_L94P_0 IO_L95N_0/GCLK7P IO_L95P_0/GCLK6S IO_L96N_0/GCLK5P IO_L96P_0/GCLK4S Pin Number D18 G18 G19 F18 F19 C19 C18 K18 J18 E19 E18
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number A14 C13 C14 K16 K15 B13 B14 F15 G15 H15 H14 A11 A12 E13 E14 J15 J14 D12 D13 F14 F13 C11 C12 B11 B12 F11 F12 D10 D11 G12 G13 B9 B10 B8 A9 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L50N_1 IO_L50P_1 IO_L49N_1 IO_L49P_1 IO_L30N_1 IO_L30P_1 IO_L29N_1 IO_L29P_1 IO_L28N_1 IO_L28P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L24N_1 IO_L24P_1 IO_L23N_1 IO_L23P_1 IO_L22N_1 IO_L22P_1 IO_L21N_1/VREF_1 IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L06N_1 IO_L06P_1 IO_L05N_1 IO_L05P_1 IO_L04N_1 IO_L04P_1/VREF_1 IO_L03N_1/VRP_1 Pin Number K14 K13 A6 A7 D9 C9 H13 H12 C7 C8 E11 E10 J13 K12 B6 B7 E8 E9 G10 G11 A4 A5 F10 G9 J12 J11 B4 B5 D6 C6 H11 J10 D8 E7 F9
Table 80: CF1144 CGA -- XQ2V6000 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L79P_1 IO_L78N_1 IO_L78P_1 IO_L77N_1 IO_L77P_1 IO_L76N_1 IO_L76P_1 IO_L75N_1/VREF_1 IO_L75P_1 IO_L74N_1 IO_L74P_1 IO_L73N_1 IO_L73P_1 IO_L72N_1 IO_L72P_1 IO_L71N_1 IO_L71P_1 IO_L70N_1 IO_L70P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L60N_1 IO_L60P_1 IO_L54N_1 IO_L54P_1 IO_L53N_1 IO_L53P_1 IO_L52N_1 IO_L52P_1 IO_L51N_1/VREF_1 IO_L51P_1
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 1 1 1 1 1 Pin Description IO_L03P_1/VRN_1 IO_L02N_1 IO_L02P_1 IO_L01N_1 IO_L01P_1 Pin Number F8 H10 H9 C2 B3 Table 80: CF1144 CGA -- XQ2V6000 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L01N_2 IO_L01P_2 IO_L02N_2/VRP_2 IO_L02P_2/VRN_2 IO_L03N_2 IO_L03P_2/VREF_2 IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2/VREF_2 IO_L22N_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L26N_2 IO_L26P_2 IO_L27N_2 E2 D2 K11 K10 F5 G5 E3 D3 J9 K9 F4 E4 E1 D1 J8 K8 H7 J7 H6 G6 L10 L9 G3 F3 G2 F2 M10 N10 J6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L27P_2/VREF_2 IO_L28N_2 IO_L28P_2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2/VREF_2 IO_L46N_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2/VREF_2 IO_L52N_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L67N_2 IO_L67P_2 IO_L68N_2 IO_L68P_2 Pin Number K6 J5 H5 L7 K7 J4 H4 G1 F1 L8 M8 J1 H2 J3 H3 M9 N9 L5 K5 K2 J2 N7 M7 L6 M6 M3 L3 L4 K4 N4 M4 M2 L2 N8 P8
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number N6 P6 P5 N5 P10 R10 P3 N3 M1 L1 P9 R9 P2 N2 R4 P4 R8 T8 T3 R3 P1 N1 T11 U11 R7 R6 U5 T5 T10 U10 U4 T4 T2 R1 U7 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L96N_3 IO_L96P_3 IO_L95N_3 IO_L95P_3 IO_L94N_3 IO_L94P_3 IO_L93N_3/VREF_3 IO_L93P_3 IO_L92N_3 IO_L92P_3 IO_L91N_3 IO_L91P_3 IO_L84N_3 IO_L84P_3 IO_L83N_3 IO_L83P_3 IO_L82N_3 IO_L82P_3 IO_L81N_3/VREF_3 IO_L81P_3 IO_L80N_3 IO_L80P_3 IO_L79N_3 IO_L79P_3 IO_L78N_3 V6 W6 V5 W5 V7 W7 V10 W10 V1 V2 W3 Y3 V9 V8 W4 Y4 W11 V11 W8 Y8 W2 Y1 AA3 AB3 Y6 Bank 2 2 2 2 2 2 2 2 2 Pin Description IO_L92P_2 IO_L93N_2 IO_L93P_2/VREF_2 IO_L94N_2 IO_L94P_2 IO_L95N_2 IO_L95P_2 IO_L96N_2 IO_L96P_2 Pin Number T7 T6 U6 U1 U2 U9 U8 U3 V4
Table 80: CF1144 CGA -- XQ2V6000 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L69N_2 IO_L69P_2/VREF_2 IO_L70N_2 IO_L70P_2 IO_L71N_2 IO_L71P_2 IO_L72N_2 IO_L72P_2 IO_L73N_2 IO_L73P_2 IO_L74N_2 IO_L74P_2 IO_L75N_2 IO_L75P_2/VREF_2 IO_L76N_2 IO_L76P_2 IO_L77N_2 IO_L77P_2 IO_L78N_2 IO_L78P_2 IO_L79N_2 IO_L79P_2 IO_L80N_2 IO_L80P_2 IO_L81N_2 IO_L81P_2/VREF_2 IO_L82N_2 IO_L82P_2 IO_L83N_2 IO_L83P_2 IO_L84N_2 IO_L84P_2 IO_L91N_2 IO_L91P_2 IO_L92N_2
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L78P_3 IO_L77N_3 IO_L77P_3 IO_L76N_3 IO_L76P_3 IO_L75N_3/VREF_3 IO_L75P_3 IO_L74N_3 IO_L74P_3 IO_L73N_3 IO_L73P_3 IO_L72N_3 IO_L72P_3 IO_L71N_3 IO_L71P_3 IO_L70N_3 IO_L70P_3 IO_L69N_3/VREF_3 IO_L69P_3 IO_L68N_3 IO_L68P_3 IO_L67N_3 IO_L67P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 Pin Number AA6 AA4 AB4 Y7 AA8 Y10 AA10 AA1 AB1 AA5 AB5 AA9 Y9 AA2 AB2 AB6 AC6 AD1 AC1 AC3 AD3 AC4 AD4 AB7 AC7 AC2 AD2 AC8 AB8 AB10 AC10 AD5 AE5 AE4 AF4 Table 80: CF1144 CGA -- XQ2V6000 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L30N_3 IO_L30P_3 IO_L29N_3 IO_L29P_3 IO_L28N_3 IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L26N_3 IO_L26P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 Pin Number AB9 AC9 AE2 AF1 AD6 AE6 AD9 AE9 AF2 AG2 AF3 AG3 AD7 AE7 AF5 AG5 AE8 AD8 AF8 AF9 AH1 AJ1 AG4 AH5 AF6 AG6 AH3 AJ3 AF7 AG7 AL1 AK1 AH2 AJ2 AJ4
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number AK4 AE10 AD10 AK2 AL2 AH6 AJ5 AE11 AF11 AK3 AL3 AF10 AG9 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L23P_4 IO_L24N_4 IO_L24P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4 IO_L26P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L28N_4 IO_L28P_4 IO_L29N_4 IO_L29P_4 IO_L30N_4 IO_L30P_4 IO_L49N_4 IO_L49P_4 IO_L50N_4 IO_L50P_4 IO_L51N_4 IO_L51P_4/VREF_4 IO_L52N_4 IO_L52P_4 IO_L53N_4 IO_L53P_4 IO_L54N_4 IO_L54P_4 IO_L60N_4 IO_L60P_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 Pin Number AE13 AM9 AL8 AP5 AP4 AG11 AG12 AN7 AN6 AL10 AL9 AF12 AF13 AK10 AK11 AP7 AP6 AH13 AH12 AJ11 AJ12 AP9 AN8 AG13 AG14 AM11 AL11 AN10 AN9 AN12 AN11 AE14 AE15 AJ13 AJ14
Table 80: CF1144 CGA -- XQ2V6000 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L19P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3/VRP_3 IO_L02P_3/VRN_3 IO_L01N_3 IO_L01P_3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
IO_L01N_4/DOUT IO_L01P_4/INIT_B IO_L02N_4/D0 IO_L02P_4/D1 IO_L03N_4/D2/ALT_VRP_4 IO_L03P_4/D3/ALT_VRN_4 IO_L04N_4/VREF_4 IO_L04P_4 IO_L05N_4/VRP_4 IO_L05P_4/VRN_4 IO_L06N_4 IO_L06P_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4/VREF_4 IO_L22N_4 IO_L22P_4 IO_L23N_4
AM4 AL5 AG10 AH11 AK7 AK8 AL6 AM6 AK9 AJ8 AM8 AM7 AN3 AM2 AJ10 AJ9 AH9 AH10 AN5 AN4 AE12
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L70N_4 IO_L70P_4 IO_L71N_4 IO_L71P_4 IO_L72N_4 IO_L72P_4 IO_L73N_4 IO_L73P_4 IO_L74N_4 IO_L74P_4 IO_L75N_4 IO_L75P_4/VREF_4 IO_L76N_4 IO_L76P_4 IO_L77N_4 IO_L77P_4 IO_L78N_4 IO_L78P_4 IO_L79N_4 IO_L79P_4 IO_L80N_4 IO_L80P_4 IO_L81N_4 IO_L81P_4/VREF_4 IO_L82N_4 IO_L82P_4 IO_L83N_4 IO_L83P_4 IO_L84N_4 IO_L84P_4 IO_L91N_4/VREF_4 IO_L91P_4 IO_L92N_4 IO_L92P_4 IO_L93N_4 Pin Number AL13 AL12 AF14 AF15 AM13 AM12 AP12 AP11 AG15 AG16 AN14 AN13 AP14 AP13 AD16 AD17 AK14 AK13 AN16 AP15 AE16 AE17 AH15 AJ15 AP17 AN17 AH17 AH16 AL15 AL14 AL16 AL17 AJ17 AJ16 AM15 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IO_L96N_5/GCLK7S IO_L96P_5/GCLK6P IO_L95N_5/GCLK5S IO_L95P_5/GCLK4P IO_L94N_5 IO_L94P_5/VREF_5 IO_L93N_5 IO_L93P_5 IO_L92N_5 IO_L92P_5 IO_L91N_5 IO_L91P_5/VREF_5 IO_L84N_5 IO_L84P_5 IO_L83N_5 IO_L83P_5 IO_L82N_5 IO_L82P_5 IO_L81N_5/VREF_5 IO_L81P_5 IO_L80N_5 IO_L80P_5 IO_L79N_5 IO_L79P_5 IO_L78N_5 IO_L78P_5 IO_L77N_5 AK18 AK19 AG18 AF18 AL18 AL19 AJ19 AJ18 AH19 AH18 AM19 AM20 AL21 AL20 AM22 AM21 AN18 AP18 AP20 AN19 AE18 AE19 AP22 AP21 AK22 AK21 AD18 Table 80: CF1144 CGA -- XQ2V6000 Bank 4 4 4 4 4 4 4 Pin Description IO_L93P_4 IO_L94N_4/VREF_4 IO_L94P_4 IO_L95N_4/GCLK3S IO_L95P_4/GCLK2P IO_L96N_4/GCLK1S IO_L96P_4/GCLK0P Pin Number AM14 AM16 AM17 AF17 AG17 AK16 AK17
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number AD19 AN22 AN21 AJ20 AH20 AG19 AG20 AP24 AP23 AL23 AL22 AF20 AF21 AM24 AM23 AJ21 AJ22 AJ24 AJ23 AN24 AN23 AN26 AN25 AL25 AL24 AE20 AE21 AN27 AP26 AP29 AP28 AG21 AG22 AN29 AN28 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L30N_5 IO_L30P_5 IO_L29N_5 IO_L29P_5 IO_L28N_5 IO_L28P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L24N_5 IO_L24P_5 IO_L23N_5 IO_L23P_5 IO_L22N_5 IO_L22P_5 IO_L21N_5/VREF_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 IO_L19P_5 IO_L06N_5 IO_L06P_5 IO_L05N_5/VRP_5 IO_L05P_5/VRN_5 IO_L04N_5 IO_L04P_5/VREF_5 IO_L03N_5/D4/ALT_VRP_5 IO_L03P_5/D5/ALT_VRN_5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B Pin Number AK24 AK25 AH23 AH22 AP31 AP30 AH24 AH25 AF22 AF23 AM27 AM26 AL27 AL26 AH26 AJ25 AN31 AN30 AK26 AK27 AG23 AF24 AM33 AN32 AJ27 AJ26 AE22 AE23 AM28 AM29 AK28 AL29 AG24 AG25 AL30
Table 80: CF1144 CGA -- XQ2V6000 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L77P_5 IO_L76N_5 IO_L76P_5 IO_L75N_5/VREF_5 IO_L75P_5 IO_L74N_5 IO_L74P_5 IO_L73N_5 IO_L73P_5 IO_L72N_5 IO_L72P_5 IO_L71N_5 IO_L71P_5 IO_L70N_5 IO_L70P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L60N_5 IO_L60P_5 IO_L54N_5 IO_L54P_5 IO_L53N_5 IO_L53P_5 IO_L52N_5 IO_L52P_5 IO_L51N_5/VREF_5 IO_L51P_5 IO_L50N_5 IO_L50P_5 IO_L49N_5 IO_L49P_5
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 5 Pin Description IO_L01P_5/CS_B Pin Number AM31 Table 80: CF1144 CGA -- XQ2V6000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 IO_L01P_6 IO_L01N_6 IO_L02P_6/VRN_6 IO_L02N_6/VRP_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 IO_L25N_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L29P_6 AE24 AD25 AJ30 AH30 AL32 AK32 AF25 AE25 AJ31 AK31 AH29 AG29 AG26 AF26 AL33 AK33 AJ32 AH32 AG28 AF28 AG30 AF30 AF29 AE29 AF27 AE27 AL34 AK34 AE28 AD28 AE26 AD26 AF31 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L67P_6 IO_L67N_6 IO_L68P_6 IO_L68N_6 IO_L69P_6 IO_L69N_6/VREF_6 IO_L70P_6 IO_L70N_6 Pin Number AG31 AF32 AG32 AC25 AB25 AJ33 AH33 AE31 AD32 AD27 AC27 AJ34 AH34 AE30 AD30 AC26 AB26 AD29 AC29 AF33 AG33 AC28 AB28 AF34 AE33 AB27 AA27 AA25 Y25 AD33 AC33 AC32 AB32 AA26 Y26
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number AD34 AC34 AC31 AD31 Y27 W27 AB29 AA29 AB31 AA31 Y28 Y29 AB33 AA33 AA30 AB30 W24 V24 AB34 AA34 W33 Y34 W25 V25 Y32 AA32 W29 V29 W28 V28 V33 V34 Y31 W31 V26 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 IO_L96P_7 IO_L96N_7 IO_L95P_7 IO_L95N_7 IO_L94P_7 IO_L94N_7 IO_L93P_7/VREF_7 IO_L93N_7 IO_L92P_7 IO_L92N_7 IO_L91P_7 IO_L91N_7 IO_L84P_7 IO_L84N_7 IO_L83P_7 IO_L83N_7 IO_L82P_7 IO_L82N_7 IO_L81P_7/VREF_7 IO_L81N_7 IO_L80P_7 IO_L80N_7 IO_L79P_7 IO_L79N_7 IO_L78P_7 IO_L78N_7 IO_L77P_7 IO_L77N_7 IO_L76P_7 U31 V31 T28 U28 U33 U34 U29 T29 U27 U26 T30 U30 R32 T32 U25 T25 R34 T33 N34 P34 U24 T24 R31 T31 N32 P32 T27 R27 N33 Bank 6 6 6 6 6 Pin Description IO_L94N_6 IO_L95P_6 IO_L95N_6 IO_L96P_6 IO_L96N_6 Pin Number V27 W30 V30 V32 W32
Table 80: CF1144 CGA -- XQ2V6000 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L71P_6 IO_L71N_6 IO_L72P_6 IO_L72N_6 IO_L73P_6 IO_L73N_6 IO_L74P_6 IO_L74N_6 IO_L75P_6 IO_L75N_6/VREF_6 IO_L76P_6 IO_L76N_6 IO_L77P_6 IO_L77N_6 IO_L78P_6 IO_L78N_6 IO_L79P_6 IO_L79N_6 IO_L80P_6 IO_L80N_6 IO_L81P_6 IO_L81N_6/VREF_6 IO_L82P_6 IO_L82N_6 IO_L83P_6 IO_L83N_6 IO_L84P_6 IO_L84N_6 IO_L91P_6 IO_L91N_6 IO_L92P_6 IO_L92N_6 IO_L93P_6 IO_L93N_6/VREF_6 IO_L94P_6
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L76N_7 IO_L75P_7/VREF_7 IO_L75N_7 IO_L74P_7 IO_L74N_7 IO_L73P_7 IO_L73N_7 IO_L72P_7 IO_L72N_7 IO_L71P_7 IO_L71N_7 IO_L70P_7 IO_L70N_7 IO_L69P_7/VREF_7 IO_L69N_7 IO_L68P_7 IO_L68N_7 IO_L67P_7 IO_L67N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7 IO_L51P_7/VREF_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 Pin Number P33 R29 R28 R26 P26 N31 P31 N30 P30 R25 P25 L34 M34 P29 N29 P27 N27 L32 M32 L31 M31 K29 L30 L33 M33 M29 L29 M28 N28 K30 K31 H32 J32 N26 M26 Table 80: CF1144 CGA -- XQ2V6000 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L46P_7 IO_L46N_7 IO_L45P_7/VREF_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L30P_7 IO_L30N_7 IO_L29P_7 IO_L29N_7 IO_L28P_7 IO_L28N_7 IO_L27P_7/VREF_7 IO_L27N_7 IO_L26P_7 IO_L26N_7 IO_L25P_7 IO_L25N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7 IO_L21P_7/VREF_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 Pin Number J33 K33 H33 J34 M27 L27 H31 J31 F32 G32 N25 M25 F34 G34 J30 H30 K28 L28 H28 J29 G29 H29 L26 K26 F33 G33 J28 J27 K27 J26 E31 F31 D32 E32 L25
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number K24 D34 E34 G30 F30 K25 J25 D33 E33 Bank 1 2 2 2 2 2 2 2 2 2 Pin Description VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 Pin Number A10 U12 T12 T1 R12 R11 R5 P12 P11 N12 N11 M11 K1 G4 AH4 AE1 AC11 AB12 AB11 AA12 AA11 Y12 Y11 Y5 W12 W1 V12 AP16 AP10 AL7 AK15 AD15 AD14 AD13 AD12
Table 80: CF1144 CGA -- XQ2V6000 Bank 7 7 7 7 7 7 7 7 7 Pin Description IO_L05N_7 IO_L04P_7 IO_L04N_7 IO_L03P_7/VREF_7 IO_L03N_7 IO_L02P_7/VRN_7 IO_L02N_7/VRP_7 IO_L01P_7 IO_L01N_7
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1
M22 M21 M20 M19 M18 L23 L22 L21 L20 E20 D28 A25 A19 M17 M16 M15 M14 M13 L15 L14 L13 L12 E15 D7 A16
2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 Pin Description VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number AC17 AC16 AC15 AC14 AC13 AP25 AP19 AL28 AK20 AD23 AD22 AD21 AD20 AC22 AC21 AC20 AC19 AC18 AH31 AE34 AC24 AB24 AB23 AA24 AA23 Y30 Y24 Y23 W34 W23 V23 U23 T34 T23 R30 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA CCLK PROG_B DONE M0 M1 M2 HSWAP_EN TCK TDI TDO TMS PWRDWN_B DXN DXP VBATT RSVD VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT AH8 D30 AJ7 AH27 AJ28 AK29 E29 F7 C31 D5 E6 AK6 F28 G27 C4 G8 AM30 AM18 AM5 V3 U32 C30 C17 C5 AD24 Table 80: CF1144 CGA -- XQ2V6000 Bank 7 7 7 7 7 7 7 7 7 Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number R24 R23 P24 P23 N24 N23 M24 K34 G31
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number AD11 AC23 AC12 AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AA22 AA13 Y22 Y13 W22 W13 V22 V13 U22 U13 T22 T13 R22 R13 P22 P13 N22 N21 N20 N19 N18 N17 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AP32 AP27 AP8 AP3 AN33 AN20 AN15 AN2 AM34 AM32 AM25 AM10 AM3 AM1 AL31 AL4 AK30 AK23 AK12 AK5 AJ29 AJ6 AH28 AH21 AH14 AH7 Bank NA NA NA NA NA NA NA NA Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number N16 N15 N14 N13 M23 M12 L24 L11
Table 80: CF1144 CGA -- XQ2V6000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AG34 AG27 AG8 AG1 AF19 AF16 AE32 AE3 AC30 AC5 AA28 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA7 Y33 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y2 W26 W21 W20 W19 W18 Table 80: CF1144 CGA -- XQ2V6000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number W17 W16 W15 W14 W9 V21 V20 V19 V18 V17 V16 V15 V14 U21 U20 U19 U18 U17 U16 U15 U14 T26 T21 T20 T19 T18 T17 T16 T15 T14 T9 R33 R21 R20 R19
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QPro Virtex-II 1.5V Military QML Platform FPGAs Table 80: CF1144 CGA -- XQ2V6000 Pin Number R18 R17 R16 R15 R14 R2 P28 P21 P20 P19 P18 P17 P16 P15 P14 P7 M30 M5 K32 K3 J19 J16 H34 H27 H8 H1 G28 G21 G14 G7 F29 F6 E30 E23 E12 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number E5 D31 D4 C34 C32 C25 C10 C3 C1 B33 B20 B15 B2 A32 A27 A8 A3
Table 80: CF1144 CGA -- XQ2V6000 Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package Specifications (1.00mm pitch)
Figure 56: CF1144 Ceramic Flip-Chip Fine-Pitch CGA Package Specifications
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QPro Virtex-II 1.5V Military QML Platform FPGAs
Revision History
This section records the change history for this module of the data sheet. Date 9/24/03 01/07/04 Version 1.0 1.1 Advance release. Initial Xilinx release. Revision
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